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Memory Strategies eBook:
COSMIC RADIATION INDUCED SER IN RAMS AND LOGIC IN ELECTRONIC SYSTEMS, 2007

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This comprehensive eBook compiles the current state of available knowledge in this timely field. Covered are an understandable exposition of the impact of cosmic radiation on soft error rate (SER) in submicron DRAMs, SRAMs and Dynamic Logic circuits. It includes discussion of many of the process, design, and system variables affecting susceptibility to this mode of error. Geographical and altitude corrections for systems data are covered as well as information on particle shielding and detection. Descriptions of device simulators currently in use to simulate the various cosmic particle effects are given along with information about companies supplying them. Various methods of accelerated test are also described such as high energy accelerators and ion beam microprobes and useful information about various vendors offering these services is included. This comprehensive report discusses results from more than 100 technical articles and publications, which are included in the extensive bibliography. 125+ pages. PDF.

OUTLINE: COSMIC RADIATION INDUCED SER IN RAMS AND LOGIC IN ELECTRONIC SYSTEMS, 2007

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Chapter 1. The Radiation Environment of The RAM
    1.1 Introduction to Cosmic Radiation Induced SER.
    1.2 Alpha Particles as Heavy Ions
    1.3 Cosmic sourced particle flux at sea level:
       1.3.1 Protons:
       1.3.2 Electrons:                       
       1.3.3 Muons:
       1.3.4 Neutrons:

Chapter 2. Cosmic Radiation Induced Soft Error Mechanisms
    2.1  Satellite Altitudes:
    2.2  Ground to Airplane Level:
       2.2.1 High energy bursts.
       2.2.2 Thermal Neutron Capture,
    2.3  Effect of  High Energy Neutrons on Induced SER   
    2.4  Multiple-Bit Soft Errors Induced by Atmospheric Neutrons       

Chapter 3. Cosmic Particle Flux Variation by Geographic Location
    3.1 Variation of Cosmic Radiation with Altitude
    3.2 Correction of Neutron Flux for Geomagnetic latitude
    3.3 Variation of Neutron Flux with Solar Cycles

Chapter 4. Design Factors Affecting SER in SRAMS
    4.1. SRAM Cell type
       4.1.1. Six Transistor Cell
       4.1.2. Resistor Load  Cell: 
       4.1.3. TFT  Cell:
    4.2. A Critical Charge Model for an SRAM
    4.3. SRAM Cell Capacitance
       4.3.1 Cell Capacitance and Critical Charge   
       4.3.2 Methods of Increasing Cell Capacitance
    4.4  Error Correction for SRAMs
       4.4.1  ECC to Reduce SER Rate for Single Bit Errors
       4.4.2   ECC for Multiple Bit Errors in SRAM 

Chapter 5. Design Factors Affecting SER in DRAMs
    5.1. DRAM Cell type
    5.2  DRAM Cell Depletion Volume Relation to Cosmic SER
    5.3  Illustration of Bitline and Cell Hit Locations in a DRAM
    5.4.  Critical Charge Models for DRAMs
        5.4.1. A Simple Critical Charge Model for Early DRAMS
        5.4.2. A Critical Charge Module for Submicron DRAMs
    5.5. SER Approximate Calculation for DRAMS:
    5.6. Mechanics of Heavy Ion Effect on DRAM Data Retention:

 Chapter 6  Device Related SER Effects
   6.1. Effect on SRAM SER of varying external system parameters:
      6.1.1. Cycle Time / Frequency, An SRAM Model
      6.1.2. Voltage Scaling
            6.1.2.1. SER Variation for Resister Load SRAMs
            6.1.2.2. SRAM SER Variation with Radiation Type and Voltage
            6.1.2.3. Embedded SRAM and Dynamic Logic with Voltage Scaling                
      6.1.3. Temperature Effects on SRAM SER
            6.1.3.1 Temperature Effects on SRAM SER for R-Load SRAMs
            6.1.3.2 Temperature Effects on SRAM SER for 6T Cell SRAMs
    6.2. Effect on DRAM SER of varying external system parameters:
      6.2.1. Effect of Operating Voltage on DRAM SER
      6.2.2. SER with Variation of Voltage and Temperature on Planar Capacitor DRAM
      6.2.3. Variation of DRAM SER with Cycle Time / Frequency
   6.3. SER variation with technology for SRAMs, DRAMs, Embedded RAMs, and 1T SRAMs
      6.3.1. SER Variation with DRAM Technology
      6.3.2. SER Variation with SRAM Technology
            6.3.2.1 Variation of SER with SRAM Collection Area.
            6.3.2.2 Effect of Change in Critical Charge by SRAM Generation
      6.3.3  SER Variation with SOI SRAM Technology
            6.3.3.1 Effect of Change in Collection Volume in SOI SRAMs
            6.3.3.2  Comparison of Bulk SRAM and SOI SRAM SER Results
      6.3.4. SER Variation with Embedded SRAM Technology
   6.4. Experiments in Neutron Induced SER Susceptibility for Non-Volatile RAMs
   6.5  SER Susceptibility of Latch Type Circuits
   6.6  SER in Processor and DSP Circuits 

Chapter 7  Process contribution to soft errors
   7.1. Radioactive contamination in Processing Materials
      7.1.1. Polonium 210
      7.1.2. Uranium 238
      7.1.3. Thorium 232
   7.2. Boron as an Alpha source in CMOS Memories:
      7.2.1. Boron doped PSG Layers:
      7.2.2. Boron Doped Buried p-layer
      7.2.3. Boron bulk dopant
   7.3. Silicon structures affecting SER 
   7.3.1. Well structure
      7.3.1.1. P-Well (and N-Well):
      7.3.1.2. Twin Well:
      7.3.1.3. Triple Well (and Quad Well):
      7.3.1.4. Retrograde well:
   7.3.2. Enhanced capacitor structures
   7.3.3. Substrate Structures
      7.3.3.1. Epitaxial Structures:
      7.3.3.2. SOI Substrates
      7.3.3.3 A Model for Estimating Neutron Induced SER in Thin Substrates.

 Chapter 8. Shielding and Detection of Cosmic Particles
   8.1. Materials that have high cross sections with neutrons.
      8.1.1. Overview of materials:
      8.1.2. Silicon:
      8.1.3. Boron 10:
      8.1.4. Cadmium:
      8.1.5  Polyethylene:
      8.1.6  Silicon dioxide
      8.1.7  Concrete
      8.1.8  Hafnium
   8.2. Shielding for Particles:
      8.2.1. Building level shielding:
      8.2.2. System level shielding
      8.2.3. Device level shielding:

Chapter 9. Cosmic Particle Accelerated Test:
    9.1. High Energy Neutron Reactors:
       9.1.1  Los Alamos Labs WNR Neutron Spallation Reactor:
       9.1.2 Sandia Pulsed III Cavity Neutron Reactor:
       9.1.3  Neutron Generator at RCNP at Osaka University
       9.1.4  Neutron Beam Facility at The Svedberg Lab (TSL)Uppsala, Sweden
    9.2. Heavy Ion Particle Reactors.
       9.2.1 Lawrence Berkeley Laboratory:
       9.2.2 Harvard High Energy Proton Reactor:
       9.2.3 LANL High Energy Proton Beam Accelerator:
       9.2.4. Synchrotron Research Center in Taiwan
       9.2.5. Brookhaven National Laboratories
       9.2.6. Tri Universities Meson Facility (Triumf):
       9.2.7. Aerospace Corporation GMIB Memory Tester
       9.2.8. Heavy Water Neutron Irradiation Facility, Kyoto Univ.
       9.2.9.  Cold Neutron Research Facility (CNRF) 
       9.2.10. IBM Analytical Services Group:
     9.3. Accelerated Device Test from Hot Radiation Sources.
     9.4. Device Failure Analysis Using Ion Beam Microprobe Reactors:
       9.4.1. Overview:
       9.4.2. Sandia Ion Beam Probe
       9.4.3. Texas Instruments and U. of North Texas, Ion beam equipment:
       9.4.4. IBM Ion Microbeam Probe:
       9.4.5. Mitsubishi Nuclear Microprobe:
     9.5. Cosmic Ray Related Accelerated System Test in Aircraft 
     9.6. Systems SER Testing at Ground Level over Time.

Chapter 10. Simulators:
   10.1. Overview:
   10.2. Commercial and Captive Device Level Simulators:
      10.2.1. DaVinci (TMA):
      10.2.2. Padre (AT&T):
      10.2.3. PISCES II (Aerospace Corp.):
      10.2.4. Sandia Labs Mixed Mode Simulator
      10.2.5. CADDETH 3-D Simulator (Hitachi)
      10.2.6. Thunder (Atlas II) Simulator (Silvaco)
      10.2.7. Intel Alpha Simulator
   10.3. Environmental Cosmic Ray SER Simulators
      10.3.1. IBM Statistical Simulator:
      10.3.2. Boeing Statistical Simulator Studies:
      10.3.3. The Fujitsu Statistical Simulator

Bibliography

Figures and Tables:              

Figure 1.1         Cosmic Particle Induced Cascade of Secondary Particles
Figure 1.2         Particle Flux for Cosmic Ray Particles at Sea Level 
Figure 2.1         Cosmic Origin Point Charge Bursts in Silicon at Sea Level
Figure 2.2         Integrated burst rate vs. induced charge in silicon
Figure 2.3         Burst Generation Rate of Neutron Induced Alphas in Silicon
Figure 2.4         Gamma Spectrum for neutron irradiated boron 10.
Figure 2.5         Neutron Cross-section vs. Energy for B10 and Au197
Figure 2.6         Relative SER vs. Cold Neutron Flux on BPSG
Figure 2.7         SRAM Operating Voltage and SER by Technology Generation
Figure 2.8         Error Rate vs. Neutron Count for Neutrons with Different Energy Spectrum Attenuated
 Table 2.1         System SER Test for 8-Mb SRAM in 180nm Technology
Figure 3.1         Flux of Cosmic Burst Neutrons by Altitude
Figure 3.2         Similarity of Neutron Energy Spectrum at Different Altitudes
 Table 3.1         Comparison of Neutron Flux for Different Altitudes and Latitudes
Figure 3.3         1-10 MeV Neutron Flux as a Function of Altitude
Figure 3.4         SER in a RAM as a Function of Atmospheric Neutron Flux
Figure 3.5         1-10 MeV Neutron Flux vs. Latitude        
Figure 3.6         Average Vertical Rigidity Cutoff  vs. Geographical Latitude
Figure 3.7         Illustration of Lines of Geomagnetic Latitude    
Figure 3.8         Illustration of Memory Subsystem SER Corrected for Altitude
 Table  3.2        Geomagnetic Correction for MTBF (Alt. vs SER vs Lat.vs Long vs Rigidity)
Figure 3.9         System SER vs. Altitude Corrected for Latitude
 Table  3.3        Periods of Extremes of Solar Activity By Year
Figure 3.10       Climax Corrected Neutron Monitor Values
Figure 4.1         6T SRAM Cell Showing Critical Junction for Charge Collection
Figure 4.2         Trends in R-Load SRAM Cell Size and Load Resistance.  
Figure 4.3         Cross Section of TFT SRAM Cell Showing Transistor in the Polysilicon Layer
Figure 4.4         Trends in Critical Charge for SRAMs
Figure 4.5         Capacitive Model of Alpha Hit on an SRAM Cell
Figure 4.6         Variation in SER with Qc for a 6T CMOS Cell
 Table  4.1        Cosmic Ray Neutron SER of an SRAM Cell(VCC vs Qcrit(n) vs.Qcrit(p) vs SER)
Figure 4.7         Capacitance Trends for MOS SRAMs
Figure 4.8         SER for a 0.35um 6T Cell SRAM vs. Critical Charge
Figure 4.9         Example of A Horizontal-Vertical Parity Scheme for Multiple Bit ECC
Figure 5.1         Cross-sections of Three Basic Types of DRAM Cells
 Table  5.1        SER From Neutron Radiation For Three Types of DRAM Cells
Figure 5.2         DRAM Cell with Associated Circuitry[114]
Figure 5.3         Equivalent Sense Amplifier Circuitry for a DRAM[58]
Figure 5.4         Neutron Induced Error Function vs. Device Critical Charge[56]        
Figure 6.1         16K and 64K SRAM SER vs. Cycle Time
Figure 6.2         Transient waveforms of high storage node potential
Figure 6.3         Model for Ave. Restored Voltage of Cycled SRAM Cell High Node.
Figure 6.4         Variation of Stored ONE Voltage with Cycle Time (VDD=5V)
Figure 6.5         Improvements in SER for a High Speed 256K SRAM
Figure 6.6         Normalized SRAM SER vs. Voltage
Figure 6.7         SER vs. Voltage for 1MB SRAM and 64K-bit Dynamic Logic Test Chips
 Table  6.1        Trends in Operating Voltage for DRAMS (Density .s V. vs. Leff vs. year)
 Table  6.2        1T SRAM SER vs. Voltage and Temperature
Figure 6.8         1T SRAM SER vs. Voltage and Temperature  
Figure 6.9         Stacked DRAM Cell Cross-Section Showing Depletion Volume        
Figure 6.10       Cosmic Induced SER for Several Generations of DRAMS
 Table  6.3        Normalized Lateral Depletion Area of Various Generations of DRAMS
Figure 6.11       SER/bit by Technology under 150MeV Proton bombardment
 Table 6.4         SER Due to Cosmic Rays for Various Memories (FITs/Mb)
Figure 6.12       Various Logic Circuits Suffering from Particle Related SER Susceptibility
 Table 6.5         Cell Sizes of Flip-Flops, SRAMs and Dual Port SRAMs in Various Technologies
Figure 6.13       Relation between sensitive nodes of flip-flop (blue) and driver of the nodes (red)
Figure 7.1         Alpha Energy Spectrum Showing 5.3 MeV Peak of Polonium
Figure 7.2         Alpha Counts vs. Collected Charge for 0.5 um 64K SRAM Test Chips
Figure 7.3         Schematic Cross-sections: (a) p-well CMOS, (b) n-well CMOS,  (c) twin well CMOS
Figure 7.4         Schematic Cross-sections of BiCMOS Quad Well and Triple Well
Figure 7.5         Illustrations of SER Improvement of Triple Well Technology
Figure 7.6         Fails in Time vs. Voltage for BiCMOS Well Structures
Figure 7.7         Cross-section of BiCMOS capacitors:(a) planar capacitor(b)stacked
Figure 7.8         Charge Generation Curves for Ions Traveling through Bulk Silicon
Figure 8.1         Neutron-Alpha Cross Section for 28Si14   
Figure 8.2         Neutron-alpha cross-section for Boron 10
Figure 8.3         Total Neutron Cross-section for Cadmium 48
Figure 8.4         Neutron Spectrum Flux Shift in a Building
Figure 9.1         Los Alamos WNR With Varying Angles for Different Energy Ranges
Figure 9.2         Neutron Spectrum at 40,000 feet and at the LANL
Figure 9.3         Layout of Neutron Beam Facility at Svedberg Lab in Uppsala, Sweden
 Table  9.1        Ion Beams Used at LBL for Cosmic Ray Studies
Figure 9.4         View of Device Under Test at Heavy Water Neutron Irradiation Facility, Kyoto U.
Figure 9.5         Simulation of LET and Range of Various Heavy Ions in Silicon[57]
Figure 9.6         Schematic of Sandia Labs Imaging System for Ion Beam Microprobe
Figure 10.1       Funnel Region of a P-Channel Device After an SEU Event
Figure 10.2       Simulation of a Neutron-Silicon Lattice Collision in a DRAM With and Without Triple Well
Figure 10.3       Simulation Methodology and Flow for Intel Alpha Induced SER Simulator
Figure 10.4       Flow Chart for the IBM Cosmic Ray Statistical Simulator
Figure 10.5       Burst Generation Rate for Various Neutron Silicon
Figure 10.6       Schematic of the AMD Statistical Simulator
Figure 10.7       Simulated latch SER Using AMD Simulator

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