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Issues in Scaling Nanotechnology SRAM
August 2007

This report discusses the various issues with scaling nanotechnology SRAMs that have been discussed as CMOS technology has scaled below 90 nm. Various methods of improving read and write stability in technologies ranging from 100 nm to 45 nm are discussed including multiple power supplies, pulsed word-line and pulsed bit-line techniques, read and write assist by raising or lowering various lines in the SRAM cell, and various process adjustments. Methods to improve SRAM stability by adding transistors to the bit-cell are discussed for both single port and dual port SRAMs to 45 nm technology. Various vertical SRAM technologies for nodes down to 32 nm are discussed including FinFET SRAMs and stacked cells with some of the 6 transistors stacked above the substrate. Various reliability issues are discussed such as minimum operating voltage drift due to NBTI, and neutron induced multi-bit soft errors. Several methods for SRAM operation at sub-threshold voltage are considered. Various leakage issues are discussed. Finally error correction and on-chip self repair are mentioned. 70+ pages.

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Issues in Scaling Nanotechnology SRAM
August 2007

Table of Contents

1.0 Background on SRAMs.
1.1 Basic Six Transistor SRAM Cell
1.2 Reading from an SRAM Cell
1.3 Writing To An SRAM Cell
1.4 Scaling an SRAM Cell Below 100 nm

2.0 Issues with Scaled Nanotechnology SRAMs
2.1 Cell Stability at low VDD
  2.1.2 SRAM Read Stability
  2.1.3 Static Noise Margin - Read Margin Issues
  2.1.4 Write Failure Issues
  2.1.5 Cell Threshold Voltage Windows With Lower VDD
  2.1.6 Dependence of VDD (min) on Temperature.

3.0 Methods To Improve Read and Write Stability From 100 nm to 65 nm
3.1 Overview of Methods to Improve Bit-Cell Stability
3.2 Multiple Power Supplies to Improve SRAM Read and Write Margins at Low Voltages
  3.2.1 Background on Use of Multiple Power Supplies
  3.2.2 Split Rail SRAM Arrays in a 65 nm Multimedia Processor
3.3 Improving Stability with Pulsed Wordline and Pulsed Bitline Schemes:
  3.3.1 Pulsed Word-line Scheme for Read:
  3.3.2 Pulsed Word-Line with Read-Modify-Write
  3.3.3 Pulsed Bit-Line Technique During Read
  3.3.4 Pulsed Bit-Line Technique During Write
  3.3.5 Boosted Word-Line Pulse for Write Assist
  3.3.6 Effect of Power Supply Noise on Dynamic SRAM Stability
3.4 Improving SRAM Read and Write Margins with Voltage Variation
  3.4.1 Read Assist by Amplifying Before Disturb
  3.4.2 Read Assist by Raising VDD Using Capacitive Coupling
  3.4.3 Write Assist by Lowering VDD For The Accessed Bit-Cell
  3.4.4 Write Assist by Raising VSS for The Bit-Cell
  3.4.5 Read Assist By Lowering the Word-Line Level
  3.4.6 Write Assist by Lowering the Bitline Voltage
  3.4.5 Read and Write Assist Circuits for Process and Temperature Variations
    3.4.5.1 Read Assist Circuit for Process and Temperature Variations
    3.4.5.2 Write Assist Circuitry for Process and Temperature Variations
3.5 Improving SRAM Write Margins with Threshold Voltage Variation
3.6 Balanced Read and Write Margins Using Dynamic VCC Switching
3.7 Improving Static Noise Margin (Read Margin) by Adjusting Threshold Implants
3.8 Improving Static Noise Margins by Applying Body Bias to The SRAM FETs

4.0 Improving SRAM Stability by Adding Transistors to the Bit-Cell
4.1 Seven Transistor Single Ended Dual Port SRAM Cell
4.2 Eight Transistor SRAM Cells
  4.2.1 Eight Transistor SRAM Cell to Eliminate Read Disturb
  4.2.2 Eight Transistor SNM Free, Sub-Threshold 65 nm SRAM Cell
  4.2.3 Eight Transistor Dual Port SRAM in 45 nm Technology
4.3 Nine Transistor SRAM Cell
4.4 Ten Transistor SRAM Cells
  4.4.1 65 nm 10T Sub-Threshold SRAM Cell
  4.4.2 130 nm Sub-Threshold 10T SRAM Cell

5.0 Process Issues and Solutions
5.1 Sources of Process Variation within the SRAM Chip
5.2 Random Dopant Fluctuations

6.0 Vertical SRAM Technologies
6.1 FinFET SRAMs
  6.1.1 Static Noise Margin of 32 nm FinFET SRAMs
  6.1.2 Spacer-defined vs. Resist-defined Fins in FinFETs in SRAMs at 32 nm
  6.1.3 Double FinFET SRAM Using TiN/HfSiOx Gate Stack for 45 nm Technology
6.2 3-D Stacked SRAM Cell

7.0 Reliability Issues in SRAMs:
7.1 Minimum Operating Voltage (Vmin) Drift
7.2 Negative Bias Temperature Instability (NBTI)
  7.2.1 Background on NBTI
  7.2.2 NBTI and Resulting Threshold Shift In SRAM Cells

8.0 SRAM Operation at Sub-Threshold Voltages
8.1 Overview of Issues for 6T SRAM Operated in Sub-Threshold Mode
8.2 Sub-Threshold Operation Using A Single Ended 6T Cell
8.3 Sub-Threshold Operation using a 10 T SRAM Cell

9.0 Leakage Issues
9.1 SRAM Leakage Issues (IDDQ fails)
9.2 Low Leakage, High Performance Embedded SRAM in 65 nm CMOS Technology
9.3 Low Leakage SRAM Using Schottky Transistors for 32 nm Node

10.0 Cell Architecture Solution

11.0 Yield, Reliability and Soft Errors
11.1 Yield Issues
11.2 Reliability Issues for SRAMs
  11.2.1 Neutron Induced Multi-bit Soft Errors in SRAMs
  11.2.2. Error Correction in SRAMs
  11.2.3 On-Chip Self Repair in SRAMs to Reduce Parametric Failures

Bibliography

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