Trends in Embedded DRAM and Floating Body DRAM, October 2009

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Trends in Embedded DRAM and Floating Body DRAM, October 2009
(1T1C, Floating Body, Unified RAM, SESO, 3T)

This report discusses companies making embedded 1T1C DRAMs in scaled geometries. It also covers development of floating body DRAMs including those using thin MOS body effects and those using parasitic bipolar junction transistor (BJT) mechanisms. Vertical FB-DRAMs in bulk technology are discussed along with some innovative unified RAM cells combining SONOS and Floating Body in a single transistor. Several ferroelectric DRAMs are in development along with three transistor gain cells including one with a single electron transistor. Various applications for IC's using embedded DRAM are noted. 70+ pages.

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Trends in Embedded DRAM and Floating Body DRAM, October 2009

Table of Contents

1.0 Overview of eDRAM Chips and Technologies

2.0 Embedded DRAM Applications and Markets

2.1 Overview of eDRAM Applications
2.2 Wireless eDRAM Applications
- 2.2.1 Overview of Wireless/Cell Phone eDRAM Applications
2.3 Consumer Entertainment Systems
2.4 Gaming Systems
- 2.4.1 Overview of Gaming System Chips with eDRAM
2.5 Televisions
- 2.5.1 MPEG-2, 422 90 nm Profile Encoder for HDTV Broadcasting
- 2.5.2 Encoder Chip for HDTV-1080p
- 2.5.3 Scan Rate Converter for Dual Channel TV Sets
2.6 High Speed Computational Systems
- 2.6.1 Power7 Microprocessor with eDRAM for SuperComputer Applications
- 2.6.2 Acalis SoC with eDRAM for U.S. Navy Security Systems

3.0 Chips Using 1T1C eDRAM with Technology and Cell Size

4.0 Companies Supplying Chips with 1T1C Embedded DRAM

4.1 IBM
- 4.1.1 Power7 MPU with 32-MB of eDRAM in 45 nm Technology (IBM)
- 4.1.2 3D Stacking of eDRAM L3 Cache over Processor with TSV (IBM)
- 4.1.3 IBM Technology Alliance
- 4.1.4 eDRAM in 45 nm Technology Logic (IBM and AMD)
4.2 NEC eDRAM
- 4.2.1 Technology Roadmap for eDRAM ( NEC)
- 4.2.2 Core 32 nm eDRAM Technology (NEC)
- 4.2.3 Core eDRAM Process in 45 nm (NEC and Toshiba)
- 4.2.4 Phase Controlled FUSI Gate Structure with HfSiON Insulator for 45 nm (NEC)
- 4.2.5 55 nm ASIC Process with eDRAM (NEC)
- 4.2.6 90 nm Logic Process with eDRAM (NEC)
- 4.2.7 130 nm eDRAM Process (NEC)
4.3 Samsung eDRAM
4.4 Sony eDRAM
4.5 Toshiba
- 4.5. 1 Some Applications Chips with eDRAM (Toshiba)
- 4.5.2 65 nm eDRAM Macro (Toshiba)
- 4.5.3 90 nm eDRAM Macro in ASIC (Toshiba)
4.6 Research in Embedded DRAM
- 4.6.1 Low Leakage MIM Capacitors Using ALD SrTiO3 (IMEC, ASM)
- 4.6.2 Programmable/Erasable MIS Capacitor using HfNO dielectric layer.

5.0 Foundaries Offering 1T1C Embedded DRAM

5.1 Chartered Semiconductor
5.2 IBM Foundry
5.3 SMIC
5.4 TSMC
- 5.4.1 Overview of 1T eDRAM Capacitors (TSMC)
- 5.4.2 65 nm MIM Capacitor eDRAM Macro (TSMC)
- 5.4.3 1T eDRAM in 90 nm Technology (TSMC)
5.5 UMC eDRAM

6.0 Introduction to Floating Body DRAM / Capacitorless DRAM

6.1 55 nm Capacitorless DRAM using Non-Overlap Structure (Samsung)
6.2 Floating Body Device on Thin SOI (Intel)
6.3 SOI Floating Body DRAM (Toshiba)
- 6.3.1 Autonomous Refresh of Floating Body Cell (Toshiba)
- 6.3.2 90 nm Fully Depleted SOI Floating Body DRAM (Toshiba)
6.4 Two Transistor Capacitorless DRAM (Renesas)

7.0 Floating Body Cells with Vertical Structures

7.1 Analytical Model of the FD Floating Body FinFET Cell (Freescale)
7.2 Vertical Double Gate Floating Body Device (Intel)
7.3 Vertical Floating Body DRAM Using a 60 nm Thyristor Structure (Qimonda)
7.4 1T eDRAM in 50 nm SOI CMOS Using Double Gate Operation (IMEP, DICE)
7.5 Optimal Cell Structures for Scaling FB-DRAMs to 25 nm Technology (Purdue U.)

8.0 FBRAM Using a Parasitic BiPolar Transistor

8.1 Planar Parasitic BiPolar Transistor FBRAM (Innovative Silicon)
8.2 FBRAM with Parasitic BiPolar Transistor on FinFET (Innovative Silicon)
8.3 Scalable Floating Body (ZRAM) cell for Long Data Retention DRAM (Hynix and ISSI)

9.0 Floating Body DRAM Architecture

9.1 Architecture of 128-Mb Chip Using Floating Body DRAM (ISSI and AMD)

10.0 Unified Memories (Non-Volatile RAMs) Using Capacitorless DRAM Technology

10.1 Schottky Barrier FinFET SONOS Unified Memory(KAIST, ETRI,Nat.Nanofab Ctr)
10.2 Overview of Unified Memory Hole Storage Methods (KAIST, and various partners)
10.3 Unified Memory Using SiGe Quantum Well for Hole Storage (KAIST, Jusung, NNC)
10.4 Unified RAM using A Partially Depleted SONOS FinFET (KAIST)
10.5 Unified FinFET Based NV-RAM Using Band Offset of Si/SiC (KAIST, EECS)
10.6 Bulk FinFET Unified RAM Cell with NVM and Capacitorless 1T-DRAM (KAIST)
10.7 SONOS FinFET 1T-DRAM on PD-SOI (KAIST)
10.8 FB-DRAM in SOONO Technology (Samsung)
10.9 SoC Using SOONO Technology for FET, DRAM and Flash (Samsung)

11.0 Multiple Transistor DRAM Cells

11.1 Three Transistor eDRAM Cell (Intel)
11.2 1-Kb 90 nm eDRAM Array Using SESO Cells (Hitachi and Renesas)

12.0 Circuit Techniques for 3T Gain Cells

12.1 Circuit Techniques for A Sub 0.9 V Logic Compatible 3T Gain Cell eDRAM

13. Ferroelectric Materials for Future DRAMS

13.1 Chain FeRAM for Non-Volatile eDRAM Cache Replacement
13.2 Ferroelectric Transistors for Use in FeDRAMS (Yale U. and SRC)

14.0 Mechanically Switched NV-RAM Memory Cell (KAIST)

15.0 Companies Offering IP in Embedded DRAM and FB-DRAM

15.1 MoSys 1T SRAM IP:
15.2 Innovative Silicon FBC (Z-RAM) Technology

Bibliography

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