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Trends in Embedded DRAM, June 2010:
1T1C, Floating Body, Unified RAM, Logic DRAM, Bipolar NPN, Thyristor RAM

This report covers 1T1C embedded DRAMs along with 1T Floating Body eDRAMs, NPN bipolar transistor eDRAM such as thyristor RAM, multiple transistor logic compatible eDRAM and eDRAM-like Ferroelectric cells. A wide range of applications for logic chips with eDRAM are reported. Various companies are already supplying chips with 1T1C eDRAM including IBM, NEC, Toshiba, Renesas/NEC, and STMicroelectronics as well as offerings from foundries with 1T1C eDRAM macros including GlobalFoundries, TSMC, IBM and UMC.. Considerable research continues of the 1T Floating Body DRAM. Companies with recent papers include: Intel discussing back gate doping at 25 nm and 15 nm replacement insulator technology for 1T-RAM, Innovative Silicon on 45 nm SOI symmetric and asymmetric doping scheme, Hynix and ISI on vertical double gate FB-RAM technology and bulk silicon technology, IMEC discussing retention time. KAIST continues its series of papers on vertical FB-eDRAM technology. Discussion fo the FB-eDRAM using the parasitic bipolar transistor effect continues with recent discussions from KAIST on avoiding unwanted parasitic bipolar transistor effect, Hynix and ISI on performance, and Samsung on basic operation and the bulk accumulation effect. Interesting research papers on 1T FB-cells included a KAIST study of optical BJT operation, a SEMETECH and Stanford study using electrons instead of holes and a Stanford study of double gate quantum well 1T eDRAM. Unified memories that include both RAM operation and NV storage in a single transistor continue to be developed. KAIST and Hynix discussed a double gate TFT unified RAM and KAIST discussed a disturbance-free unified 1T RAM. Logic-compatible transistor-based eDRAM cells continue to be developed with the U. of Minnesota discussing a 65 nm 2T gain cell with 110us retention and Samsung discussed circuit techniques for sub 0.9V logic compatible 3T gain cell eDRAM. Embedded DRAM cells using NPN bipolar transistors are also in development. KAIST discussed a gateless NPN silicon nanowire and Global Foundries is in development with T-RAM on 32nm and 22 nm devices and also discussed a logic process compatible cell using a MOS capacitor with an open base NPN bipolar transistor. T-RAM presented a reliability study of 130 nm SOI Thyristor memory. Ferroelectric eDRAMs of the Chain FeRAM type were discussed by Toshiba and Yale U. and Semiconductor Research Corp. researched a 10nm FeDRAM with long data retention.

100+ pages

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Table of Contents

1.0 Overview of eDRAM Cells, Chips, Applications and Technologies

2.0 Embedded DRAM Applications

• 2.1 Overview of eDRAM Applications
• 2.2 Mobile Graphics Systems
  • 2.2.1 Intelligent Buffer IC's for Mobile Graphics Systems
  • 2.2.2 Mobile Graphics Display Panel Chips
• 2.3 Wireless and Handheld Devices
• 2.4 Gaming Systems
  • 2.4.1 Overview of Gaming System Chips with eDRAM
• 2.5 Televisions
  • 2.5.1 Real Time Encoder for HDTV-1080p with eDRAM
• 2.6 High Speed Computational Systems
  • 2.6.1 Power7 Microprocessor with eDRAM for SuperComputer Applications
  • 2.6.2 Acalis SoC with eDRAM for U.S. Navy Security Systems
• 2.7 Secure Processor Systems
• 2.8 Read Recording Channel IC's
• 2.9 Network Processors

3.0 Chips Using 1T1C eDRAM with Technology and Cell Size

4.0 Companies Developing Chips with 1T1C Embedded DRAM

• 4.1 IBM
  • 4.1.1. In-Situ Measurement of Variability in 45 nm SOI eDRAM (IBM)
  • 4.1.2 32 nm SOI eDRAM Technology (IBM)
  • 4.1.3 Power7 MPU with 32-MB of eDRAM in 45 nm Technology (IBM)
  • 4.1.4 Wire Speed Power Processor with eDRAM in 45 nm Technology(IBM)
  • 4.1.5 3D Stacking of eDRAM L3 Cache over Processor with TSV (IBM)
  • 4.1.6 Hierarchical Differential Sense Amplifier for DRAM Arrays IBM)
  • 4.1.7 IBM Technology Alliance
  • 4.1.8 eDRAM in 45 nm Technology Logic (IBM and AMD)
• 4.2 LSI Logic
• 4.3 Renesas/NEC eDRAM
  • 4.3.1 NEC Announced eDRAM Chips
  • 4.3.2 NEC 28 nm Process for Consumer SoC with eDRAM
  • 4.3.3 Core 32 nm eDRAM Technology (Renesas/NEC)
  • 4.3.4 90 nm Logic Process with eDRAM (Renesas/NEC)
• 4.4 Rohm
• 4.5 Sony
• 4.6 STMicroelectronics
• 4.7 Toshiba
  • 4.7.1 65 nm eDRAM Macro (Toshiba)
  • 4.7.2 90 nm eDRAM Macro in ASIC (Toshiba)

5.0 Research in Embedded DRAM

• 5.1 Thermal Analysis of different types of caches (Purdue University)
• 5.2 N-bit Macrocell with 1 SRAM Cell and n-1 DRAM Cells (U. Petitec de Valencia)
• 5.3 eDRAM Testing (National Chiao-Tung University)
• 5.4 45 nm Low Power ePSRAM Using ECC for Self-Refresh Scheme (Sungkyunkwan U.)
• 5.5 Low Leakage MIM Capacitors Using ALD SrTiO3 (IMEC, ASM)

6.0 Foundries Offering 1T1C Embedded DRAM

• 6.1 Overview of Foundries with eDRAM
• 6.2 Global Foundries /Chartered Semiconductor
  • 6.2.1 Global Foundries Integrated Operations with Chartered Semiconductor
  • 6.2.2 Global Foundries 22 nm Technology and Embedded RAM
  • 6.2.3 Global Foundries Developing Thyrister RAM for 32 nm and 22 nm Technologies
  • 6.2.4 Global Foundries 40 nm Bulk Silicon Technology with eDRAM
  • 6.2.5 Global Foundries/Chartered 1T-SRAM in 90 nm Technology
• 6.3 IBM Foundry
  • 6.3.1 Embedded DRAM in 32 nm and 22nm SOI technology (IBM)
• 6.4 TSMC (eDRAM)
  • 6.4.1 Overview of 1T eDRAM Capacitors (TSMC)
  • 6.4.2 65 nm MIM Capacitor eDRAM Macro (TSMC)
  • 6.4.3 1T eDRAM in 90 nm Technology (TSMC)
  • 6.4.4 Soft Error Reliability of eDRAM with Scaling (TSMC)
• 6.5 UMC eDRAM

7.0 Introduction to Floating Body DRAM / Capacitorless DRAM

• 7.1 Integration of Back-Gate Doping for 15nm FB Cell (Intel)
• 7.2 Doping Schemes for 45 nm SOI FB-DRAM (Innovative Silicon)
• 7.3 Operating Characteristics and Retention of 50 nm FB-DRAM Cells (Innovative Silicon)
• 7.4 FB-eDRAM Using FD SOI and GIDL Write Current (STMicroelectronics)
• 7.5 55 nm Capacitorless DRAM using Non-Overlap Structure (Samsung)
• 7.6 Floating Body Device on Thin SOI (Intel)
• 7.7 SOI Floating Body DRAM (Toshiba)
  • 7.7.1 Autonomous Refresh of Floating Body Cell (Toshiba)
• 7.8 Two Transistor Capacitorless DRAM (Renesas)

8.0 Floating Body Cells with Vertical Structures

• 8.1Vertical Double Gate "Z-RAM" Technology with Low Voltage Operation (Hynix, ISI)
• 8.2 Retention times of 10s for bulk FinFET 1T-DRAM Devices (IMEC)
• 8.3 A Silicon on Replacement Insulator FB-Cell Memory on Bulk Substrate (Intel)
• 8.4 Floating Body Cell on Bulk Silicon Using 3D Structures (Innovative Silicon, Hynix)
• 8.5 Effect of FinFET Transistors Used for FB-RAM Operation on SOI (Vanderbilt U.)
• 8.6 Isolation Dielectric Effects of PDSOI FinFET on Capacitorless 1T-DRAM (KAIST)
• 8.7 Analytical Model of the FD Floating Body FinFET Cell (Freescale)
• 8.8 Vertical Double Gate Floating Body Device (Intel)
• 8.9 1T eDRAM in 50 nm SOI CMOS Using Double Gate Operation (IMEP, DICE)

9.0 Floating Body RAM Using a Parasitic BiPolar Transistor

• 9.1 Overview of Planar Parasitic BiPolar Transistor FBRAM (Innovative Silicon)
• 9.2 BJT 1T DRAM That Avoids Unwanted Parasitic BJT Activation (KAIST)
• 9.3 Scalable Floating Body (ZRAM) cell for Long Data Retention DRAM (Hynix and ISSI)
• 9.4 Physical Insights into BJT-Based 1T DRAM Cells (Samsung, U. of Florida)

10.0 Floating Body DRAM Architecture and Circuits

• 10.1 Some Peripheral Circuits for FinFET based FB-RAM (IMEC)
• 10.2 Architecture of 128-Mb Chip Using Floating Body DRAM (ISSI and AMD)

11.0 Reliability, Test and Modeling of FB-DRAM

• 11.1 Comparative Endurance of "Z-RAM" (Innovative Silicon)
• 11.2 Data Retention Improvement in 1T DRAM Cell (Seoul Nat. University)
• 11.3 SPICE Model for Modeling FB-DRAM (Innovative Silicon)

12.00 Research in 1T Capacitorless eDRAMs

• 12.1 Optical 1T DRAMs Based on BJT Operation (KAIST)
• 12.2 1T DRAM Cell Using Electrons (SEMATECH and Stanford Univ.)
• 12.3 Capacitorless Double Gate Quantum Well 1T eDRAM

13.0 Unified Memories (Non-Volatile RAMs) Using Capacitorless DRAM Technology

• 13.1 Unified RAM with Poly-Channel TFT with Separated Double Gate (KAIST and Hynix)
• 3.2 Double Gate Unified 1T DRAM with NV Function (Kyungpook Nat.U., Keoul Nat. U)
• 13.3 Unified RAM Using 1T-DRAM and ReRAM (KAIST)
• 13.4 Unified Memory Using 1T Floating Body DRAM and SONOS NV (Kyungpook Nat. U.)
• 13.5 Schottky Barrier FinFET SONOS Unified Memory (KAIST, ETRI,Nat.Nanofab Ctr)
• 13.6 Overview of Unified Memory Hole Storage Methods (KAIST, and various partners)
• 13.7 Unified Memory Using SiGe Quantum Well for Hole Storage (KAIST, Jusung, NNC)
• 13.8 Unified RAM using A Partially Depleted SONOS FinFET (KAIST)
• 13.9 Unified FinFET Based NV-RAM Using Band Offset of Si/SiC (KAIST, EECS)
• 13.10 Bulk FinFET Unified RAM Cell with NVM and Capacitorless 1T-DRAM (KAIST)
• 13.11 FB-DRAM in SOONO Technology (Samsung)
• 13.12 SoC Using SOONO Technology for FET, DRAM and Flash (Samsung)

14.0 Logic Compatible Transistor Based DRAM Cells

• 14.1 Logic eDRAM Using 65 nm 2T Gain Cell with 110 us Retention (U. of Minnesota)
• 14.2 Circuit Techniques for A Sub 0.9 V Logic Compatible 3T Gain Cell eDRAM
• 14.3 Three Transistor eDRAM Cell (Intel)
• 14.4 1-Kb 90 nm eDRAM Array Using SESO Cells (Hitachi and Renesas)

15.0 Embedded DRAM Cells using NPN BiPolar Transistor

• 15.1 Bistable Resistor gateless NPN Silicon Nanowire Memory (KAIST)
• 15.2 EDRAM Cell MOS Capacitor and NPN Bipolar Transistor (Global Foundries)
• 15.3 Thyristor RAM and Thyristor-Like Embedded RAMs
  • 15.3.1 Thyristor RAM Development for 32 nm and 22 nm Technology
  • 15.3.2 Reliability Study of Thyristor RAM Devices (T-RAM)

16.0 Ferroelectric Materials for Future DRAMS

• 16.1 Chain FeRAM for Non-Volatile eDRAM Cache Replacement
• 16.2 Ferroelectric Transistors for Use in FeDRAMS (Yale U. and SRC)

17.0 Mechanically Switched NV-RAM Memory Cell (KAIST)

18.0 Companies Offering IP in eDRAM and eDRAM-Like Technologies

• 18.1 MoSys (1T SRAM) IP
• 18.2 Innovative Silicon FBC (Z-RAM) Technology
• 18.3 T-RAM (Thyristor RAM Technology)

Bibliography

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