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Trends in Embedded DRAM, August 2011
1T1C MIM and Trench, Floating Body, Unified RAM, Logic Gain DRAM, Bipolar NPN, Thyristor-based RAM

Active work in embedded DRAM is ongoing with many companies, foundries, labs and universities developing either the traditional 1T1C eDRAM cell either stacked or trench, the floating body eDRAM cell, the BJT parasitic transistor 1T cell, thyristor-like 1T eDRAM cells, the multitransistor logic compatible eDRAM or the stacked 3D TSV eDRAM.

Development work in 1T1C eDRAM is ongoing in 32 to 45 nm technology nodes. Reliability and test effort in 1T1C eDRAM includes work on BIST, voltage contrast inspection, thermal analysis and SER. Support circuits are in development. 1T1C eDRAMs in are being described in various processors. Several companies and foundries are in production with eDRAM.

Inspite of the demise of one of the early developers in 1T capacitorless eDRAM, advances in this area continue with many innovations particularly in bulk floating body cells and vertical configurations including FinFET type cells. Efforts continue in parasitic Bipolar Junction Transistor (BJT) 1T eDRAM. Architecture and circuits are being developed and much reliability, test and modeling is being done.

Unified memories continue to be explored using various 1T eDRAM concepts. Logic compatible transistor based cells are being investigated and NPN bipolar transistor cells such as thyristor based devices are still under investigation. Much effort is also ongoing in 3D TSV chip stacking to avoid embedded the DRAM on the chip with the high performance logic device.   125+ pages

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Table of Contents

1.0 Overview of Embedded DRAM Trends

2.0 Embedded DRAM Applications

• 2.1 Overview of eDRAM Applications
• 2.2 Mobile Graphics and Gaming Systems
  • 2.2.1 Nintendo Wee U in 45 nm SOI
  • 2.2.2 Intelligent Buffer IC's for Mobile Graphics Systems
• 2.3 Wireless and Handheld Devices
• 2.4 Gaming Systems
  • 2.4.1 Overview of Gaming System Chips with eDRAM
• 2.5 Multi-Core Processors with eDRAM
  • 2.5.1 Using Trench eDRAM in Multicore Processors (IBM)
• 2.6 Televisions
  • 2.6.1 Real Time Encoder for HDTV-1080p with eDRAM (Fujitsu, NEC, Toshiba, Nemochips)
• 2.7 High Speed Computational Systems
  • 2.7.1 Power7 Microprocessor with eDRAM for SuperComputer Applications
• 2.8 Secure Processor Systems
• 2.9 Read Recording Channel IC's
• 2.10 Network Processors
• 2.11 Audio Control Microcontroller

3.0 1T1C eDRAM

• 3.1 Chips Using 1T1C eDRAM with Technology and Cell Size
• 3.2 1T1C eDRAM Technology
  • 3.2.1 45 nm Technology for Processor and L3 Cache (IBM)
  • 3.2.2 eDRAM in Commercial 95 nm DRAM Process (Micron Japan)
  • 3.2.3 A 200 MHz 40 nm eDRAM Process with Three Added Critical Masks (TSMC)
  • 3.2.4 eDRAM Cell for Use in NAND Flash Memory Buffers (Toshiba)
  • 3.2.5 32-MB L3 Cache 45 nm SOI DT eDRAM Macro for "Power7 Processor (IBM)
  • 3.2.6 MIM eDRAM Capacitor in Low-K Film for 28 nm Logic Node (Renesas)
  • 3.2.7 eDRAM Cell Architecture in 45 nm Technology Node (STMicroelectronics)
  • 3.2.8 Key Technologies for eDRAM Cells to 40 nm (Renesas)
  • 3.2.9 Embedded DRAM in 32 nm Bulk Silicon (STMicroelectronics)
  • 3.2.10 0.039 um2 Deep Trench 32 nm eDRAM Cell in High-K/Metal SOI Technology (IBM)
• 3.3 1T1C eDRAM Reliability and Test
  • 3.3.1 Improved Jg Leakage 0.4 nm EOT STO-based MIM Capacitor (IMEC, K.U.Leuven)
  • 3.3.2 Memory BIST Based on Configurable Spares (Nat. Tsinghua Univ.)
  • 3.3.3 eDRAM Test in 45 nm Technology (IBM)
  • 3.3.4 BIST for eDRAM and Standalone DRAM (Politec. di Torino)
  • 3.3.5 Using Voltage Contrast Inspection to Detect Deep Trench eDRAM Faults (IBM)
  • 3.3.6 AFP Characterization of eDRAM Processes to 20nm in Real Time (IBM)
  • 3.3.7. In-Situ Measurement of Variability in 45 nm SOI eDRAM (IBM)
  • 3.3.8 Thermal Analysis of different types of caches (Purdue University)
  • 3.3.9 eDRAM Testing (National Chiao-Tung University)
  • 3.3.10 Soft Error Reliability of eDRAM with Scaling (TSMC)
• 3.4 Support Circuits for 1T1C eDRAM
  • 3.4.1 BL Sense Amp for 4F2 40 nm Stacked DRAM with 10 fF Capacitor (Hitachi)
  • 3.4.2 eDRAM 32 nm Capacitor over Low-K Bitcell Architecture (STMicroelectronics)
  • 3.4.3 45 nm Low Power ePSRAM Using ECC for Self-Refresh Scheme (Sungkyunkwan U.)
  • 3.4.4 Hierarchical Differential Sense Amplifier for DRAM Arrays

4.0 1T1C eDRAM in Processor and Other Logic Chips

• 4.1 Architecture of the IBM "Power7" with eDRAM L3 Cache (IBM)
• 4.2 Using Trench eDRAM in Multicore Processors (IBM)
• 4.3 Power7 MPU with 32-MB of eDRAM in 45 nm Technology (IBM)
• 4.4 eDRAM Chips for Graphics Processors (NEC)
• 4.5 Wire Speed Power Processor with eDRAM in 45 nm Technology (IBM)
• 4.6 eDRAM in Magnetic Recording Read Channel IC's (LSI, Rensselaer)
• 4.7 eDRAM in PowerPC Processors (LSI Logic)
• 4.8 N-bit Macrocell with 1 SRAM Cell and n-1 DRAM Cells (U. Politec de Valencia)

5.0 Companies Developing or Supplying Chips with 1T1C Embedded DRAM

• 5.1 IBM
• 5.2 LSI Logic
• 5.3 Micron
• 5.4 Renesas/NEC eDRAM
• 5.5 Rohm
• 5.6 Samsung eDRAM
• 5.7 STMicroelectronics
• 5.8 Toshiba

6.0 Foundries Offering 1T1C Embedded DRAM

• 6.1 Overview of Foundries with eDRAM
• 6.2 Global Foundries /Chartered Semiconductor
  • 6.2.1 Global Foundries Integrated Operations with Chartered Semiconductor
  • 6.2.2 22 nm Technology and Embedded RAM (Global Foundries)
  • 6.2.3 Developing Thyrister RAM for 32 nm and 22 nm Technologies (Global Foundries)
  • 6.2.4 40 nm Bulk Silicon Technology with eDRAM (Global Foundries)
  • 6.2.5 1T-SRAM in 90 nm Technology (Global Foundries)
• 6.3 IBM Foundry
• 6.4 TSMC (eDRAM)
  • 6.4.1 Overview of 1T eDRAM Capacitors (TSMC)
  • 6.4.2 40 nm Technology (TSMC)
  • 6.4.3. 55 nm Technology (TSMC)
  • 6.4.4 65 nm MIM Capacitor eDRAM Macro (TSMC)
  • 6.4.5 Soft Error Reliability of eDRAM with Scaling (TSMC)
• 6.5 UMC Foundry eDRAM

7.0 Floating Body DRAM/ 1T Capacitorless DRAM

• 7.1 Introduction to Floating Body DRAM / Capacitorless DRAM
• 7.2 Two Programming Mechanisms for 1T-DRAM FD-SOI Cells (CEA/LETI)
• 7.3 Integration of Back-Gate Doping for a 15nm FB Cell (Intel)
• 7.4 Operating Characteristics and Retention of 50 nm FB-DRAM Cells (Innovative Silicon)
• 7.5 FB-eDRAM Using FD SOI and GIDL Write Current (STMicroelectronics)
• 7.6 Two Transistor Capacitorless DRAM (Renesas)

8.0 1T Floating Body Cells with Vertical Structures

• 8.1 22 nm 1T eDRAM Cell For Bulk and SOI Substrates (U. of Granada)
• 8.2 Double Heterojunction Vertical 1T DRAM with Si/SiGe Heterojunctions (Kookmin U.)
• 8.3 Offset Buried MG Vertical FB Cell on Recess Gate DRAM Technology (Hynix)
• 8.4 Vertical Channel 1T-DRAM with Middle Partial Insulation (Nat. Sun Yat-Sen Univ.)
• 8.5 1T-DRAM Cell with Partitioned Body (Univ. de Granada)
• 8.6 Vertical Double Gate Technology with Low Voltage Operation(Hynix, ISI)
• 8.7 Floating Body Cell on Bulk Silicon Using 3D Structures (Innovative Silicon, Hynix)
• 8.8 Vertical FinFET 1T-DRAM Devices
  • 8.8.1 Effect of Substrate Bias on Characteristics of Bulk FinFET 1T-DRAM Cell (IMEC)
  • 8.8.2 Retention times of 10s for bulk FinFET 1T-DRAM Devices (IMEC)
  • 8.8.3 Isolation Dielectric Effects of PDSOI FinFET on Capacitorless 1T-DRAM (KAIST)
  • 8.8.4 Effect of FinFET Transistors Used for FB-RAM Operation on SOI (Vanderbilt U.)
• 8.9 A Silicon on Replacement Insulator FB-Cell Memory on Bulk Substrate (Intel)

9.0 Floating Body RAM Using a Parasitic BiPolar Transistor

• 9.1 Overview of Planar Parasitic BiPolar Transistor FBRAM
• 9.2 Bipolar Transistor Simulation for Bulk Substrate 1T eDRAM(STM, IM2NP, CNRS, TCG)
• 9.3 Fin Width Dependence of BJT Based 1T FinFET DRAM (KAIST)
• 9.4 Operation of Double Gate Bipolar Operation 1T DRAM cells(U. of Calabria)
• 9.5 BJT 1T DRAM That Avoids Unwanted Parasitic BJT Activation (KAIST)
• 9.6 Doping Schemes for 45 nm SOI BJT FB-DRAM (Innovative Silicon)
• 9.7 Floating Body BJT 1T-DRAM Cell for Long Data Retention DRAM (Hynix and ISI)
• 9.8 Physical Insights into BJT-Based 1T DRAM Cells (Samsung, U. of Florida)

10.0 Floating Body DRAM Architecture and Circuits

• 10.1 Some Peripheral Circuits for FinFET based FB-RAM (IMEC)
• 10.2 Architecture of 128-Mb Chip Using Floating Body DRAM (ISSI and AMD)

11.0 Reliability, Test and Modeling of FB-DRAM

• 11.1 Characterization Technique for FB Devices Using Optically Generated Carriers(KAIST)
• 11.2 Capacitorless 1T DRAM with Improved Data Retention (Sogang Univ.)
• 11.3 Effect of Total ionizing Dose Effects on FinFET 1T-DRAMs (Vanderbilt University)
• 11.4 Modeling a 50 nm Floating Body DRAM Cell (Technical Univ. of Vienna)
• 11.5 Data Retention Improvement in 1T DRAM Cell (Seoul Nat. University)
• 11.6 Comparative Endurance of "Z-RAM" (Innovative Silicon)
• 11.7 SPICE Model for Modeling FB-DRAM (Innovative Silicon)

12.0 Research in 1T Capacitorless eDRAMs

• 12.1 Trench Oxide TFT 1T-DRAM (Nat. Sun Yat-Sen Univ.)
• 12.2 1T-DRAM Using Light Assist for Optical Systems (KAIST)
• 12.3 1T DRAM FET with Non-Overlap Structure and Recessed Channel (Seoul Nat. Univ.)
• 12.4 1T DRAM Cell Using Electrons (SEMATECH and Stanford Univ.)
• 12.4 Capacitorless Double Gate Quantum Well 1T eDRAM

13.0 Unified Memories (Non-Volatile RAMs) Using Capacitorless DRAM Technology

• 13.1 20 nm Surrounding Gate URAM Using 8 nm Nanowire on Bulk Substrate (KAIST)
• 13.2 Unified RAM with Poly-Channel TFT with Separated Double Gate (KAIST and Hynix)
• 13.3 Double Gate 1T DRAM with NV Function (Kyungpook Nat.U., Keoul Nat. U)
• 13.4 Unified RAM Using 1T-DRAM and ReRAM (KAIST)
• 13.5 Unified Memory Using 1T Floating Body DRAM and SONOS NV (Kyungpook Nat. U.)
• 13.6 Unified RAM using A Partially Depleted SONOS FinFET (KAIST)
• 13.7 SoC Using SOONO Technology for FET, DRAM and Flash (Samsung)

14.0 Companies Investigating 1T Capacitorless DRAM Cells

• 14.1 Hynix
• 14.2 STMicroelectronics
• 14.3 Renesas
• 14.4 Intel

15.0 Logic Compatible Transistor Based DRAM Gain Cells

• 15.1 Preferential Boosting of 3T Gain Cell eDRAM (University of Minnesota)
• 15.2 A Logic Compatible 700 MHz 2T1C eDRAM Using Only Thin Oxide (U. of Minnesota)
• 15.3 Dual Transistor 2T eDRAM Cell for Low Power Applications (Univ. of Michigan)
• 15.4 Using Variation of eDRAM Gain Cell to Improve Design (U. of Minnesota)
• 15.5 Logic eDRAM Using 65 nm 2T Gain Cell with 110 us Retention (U. of Minnesota)
• 15.6 3T Boosted eDRAM Gain Cell (U. of Minnesota)
• 15.7 Circuit Techniques for Sub 0.9 V Logic Compatible 3T Gain Cell eDRAM (Samsung)

16.0 Embedded DRAM Cells using NPN BiPolar Transistor

• 16.1 Bistable Resistor Gateless NPN Silicon Nanowire Memory (KAIST)
• 16.2 EDRAM Cell MOS Capacitor and NPN Bipolar Transistor (Global Foundries)
• 16.3 Thyristor RAM and Thyristor-Like Embedded RAMs
• 16.3.1 Thyristor RAM Technology Embedded in 32 nm Logic (T-RAM)
• 16.3.2 Thyristor RAM Development for 32 nm and 22 nm Technology
• 16.3.3 Reliability Study of Thyristor RAM Devices (T-RAM)

17.0 3D Chip Stacking of DRAM/Processors Using TSV and Redistribution Wiring

• 17.1 32 nm 3D TSV Stackable High-K/Metal Gate SOI eDRAM
• 17.2 3D TSV Integration of eDRAM in High End Server Systems (IBM)
• 17.3 Temp, Refresh Period and ECC Effects on Reliability of 3D Stacked eDRAM (KAIST)
• 17.4 1-Tbyte/s 1 Gbit 3D TSV DRAM Stacked with Multicore Processor (Hitachi)
• 17.5 Improving Peak Performance of 3D Stacked DRAM (Postech)
• 17.6 Chip Stacking Using Fine Pitch Bumps Using DRAM and Processor SiP (Toshiba)
• 17.7 3D Stacking of eDRAM L3 Cache over Processor with TSV (IBM)

Bibliography

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