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A Memory Strategies Focus Report on MRAM - New Report for 2010

Magnetic RAM (MRAM) Product, Technology, R&D August 2010
(STT-MRAM, Field Write MRAM, M-CMOS Logic, Multi-Bit, M-FPGA, Test, Applications, Roadmaps, Reliability, Modeling, Architecture)

The Magnetic RAM is an emerging memory technology that is fast, random access, non-volatile and rad hard. It has potential to serve some applications currently served by traditional memories such as embedded SRAM and NOR Flash, and perhaps in scaled generations to replace DRAMs, and even NAND flash. Two main types of MRAM are being developed today. The field write MRAM writes by using the field around a current line to flip the polarization of a magnet. It has been around now for more than 10 years and is currently in production as a standalone 16-Mb and in late development as an embedded memory. The primary issue with the field write MRAM is the high write current which makes scaling difficult. The spin transfer torque (STT) MRAM, which uses lower current polarized electron spin to write, is in development by many companies, labs and universities, but is not yet in production. Technology types include in-plane and perpendicular-to- plane magnetism. Issues being explored include a switching current asymmetry effect and thermal instability during write. Several companies are discussing thermal assist (TAS) MRAMs which are heated during programming to reduce the write current. Multi-level cells to improve density have been shown. Uses for the MRAM in programmable logic circuits is also being explored as are spin polarized domain wall motion MRAMs.

140+ pages.

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Table of Contents - Magnetic RAM Product, Technology, R&D August 2010

1.0 Overview of Current MRAM Product, Development and Technology

2.0 Current and Projected Magnetic RAM Applications

• 2.1 Overview of Propective MRAM Applications
  • 2.1.1 SRAM Replacement
  • 2.1.2 NOR Flash Replacement
  • 2.1.3 DRAM Replacement Applications
  • 2.1.4 NAND Flash Applications
• 2.2 Industrial Applications
  • 2.2.1 Serial Peripheral Interface Applications
  • 2.2.2 Industrial Touch-Screen Application
  • 2.2.3 Small Industrial Applications
• 2.3 Consumer Applications
  • 2.3.1 Portable Multimedia Applications
  • 2.3.2 Mobile Phone MRAM Applications
  • 2.3.3 Low Power Mobile Applications
• 2.4 Aerospace and Military Applications
  • 2.4.1 Flight Control Computers in Airplanes
  • 2.4.2 Space and Military Applications
• 2.5 Networking and Server Applications
• 2.6 Cache in Graphics Processing Units with Small Number of Writes

3.0 MRAM Production Roadmaps

• 3.1 Announced Production and Prototyping for Various MRAM Developers
• 3.2 MRAM Production, Manufacturing and Financial Announcements
  • 3.2.1 Avalanche Technology
  • 3.2.2 Crocus MRAM IP:
  • 3.2.3 EverSpin Field Write MRAM
  • 3.2.4 Grandis STT-RAM
  • 3.2.5 Hitachi Spin Transfer Torque MRAM (SPRAM)
  • 3.2.6 Hynix STT-RAM
  • 3.2.8 NEC MRAM
  • 3.2.9 Renesas Embedded MRAM:
  • 3.2.10 Samsung STT MRAM
  • 3.2.11 Toshiba Perpendicular STT MRAM
  • 3.2.12 TSMC

4.0 Overview of MRAM and Spintronic Theory

• 4.1 Theory of Field Programmed MRAMs
• 4.2 Theory of Spin Programmable MRAM

5.0 Field Switching MTJ MRAM Devices

• 5.1 16-Mb Field Switching MRAM in 180 nm Technology (Everspin)
• 5.2 Shape-Varying MTJ with Inserted Write Line (NEC)
• 5.3 Field Programmed Perpendicular MRAM With Pole Structure (Pusan National U)

6.0 Methods for Lowering MTJ MRAM Write Current in Field Switching MRAMs

• 6.1 Effect of MTJ Edge Deformation on Switching Current
• 6.2 Diamond Shaped Field Programmed MRAM Elements (U. of Alabama)
• 6.3 2T1MJT Cell for Write Current Control (NEC)

7.0 Embedded Field Programmed MRAM in Conventional CMOS Logic

• 7.1 MRAM L2 Cache Stacked on Multiprocessor
• 7.2 Embedded MRAM to Replace SRAM in SoC
• 7.3 Magnetic Primitive Cell for SoC Libraries Using MRAM/CMOS Process (NEC)
• 7.4 Dual Port 5T2MTJ Cell in SoC MRAM Technology (NEC)

8.0 Test, Reliability and Modeling in MTJ Field Switching MRAMs

• 8.1 Verilog-A Model for Toggle Mode MRAM (Oregon State Univ.)
• 8.2 Formula for Saturation Field for Toggle Mode MRAM (AIC University)
• 8.3 SPICE Model of Field Programmable MRAM Circuit (Rochester Inst. of Tech)
• 8.4 Technique for Evaluating Write Disturb Robustness in Toggle Mode MRAMs (NEC)
• 8.5 Using Systematic Tools for MRAM Analysis (Nat. Tsing Hua University)
• 8.6 Write Disturb Faulting Modeling for Toggle Mode MRAM(Nat. Tsing Hua Univ.)
• 8.7 Correlation Study Between Electrical and Magnetic Properties of MTJ

9.0 Theory of Spin Transfer Switching MRAM (STT MRAM)

• 9.1 Spin Injection from thin Fe film into silicon (Naval Research Lab.)
• 9.2 Spin Transfer Torque MRAM/SPRAM (Hitachi)
• 9.3 Spin-Torque Transfer (STT) RAM (Grandis)

10.0 Spin Transfer Torque (STT) MRAM Device, Design, and Process

• 10.1 Multi-Level Cell STT-MRAM with Series Connected MTJs (Hitachi, Tohoku U.)
• 10.2 Read and Restore for G-bit STT MRAM to Replace DDR SDRAM (Hitachi)
• 10.3 3-Terminal STT MRAM with Separated Read&Write Operations(IBM-MagIC)
• 10.4 Spin-Transfer Precessional Switching with Sub-ns I Pulse(INAC/SPINTEC,CEA)
• 10.5 Improving Density of STT MRAM with Current Threshold Variability (Rensselaer)
• 10.6 32-Mb 2T1R STT-MRAM "SPRAM" with 300 uA/cell Write (Hitachi, Tohoku U.)
• 10.7 Combination Spin-Torque and Field Programmable MRAM (Hitachi)

11.0 Source Degeneration Effect and Current Asymmetry Issue in STT MRAM

• 11.1 STT-MRAM with Top Pinned Cell For Write Current Asymmetry Issue (Fujitsu)
• 11.2 SAF Ref. layer in MTJ to Reduce Asymmetry Causing Reversal(Crocus, Spintec)
• 11.3 Theory of Switching Current Asymmetry of MTJs in STT MRAMs (Qualcomm)
• 11.4 45 nm STT eMRAM Solving Source Degeneration Issue(TSMC, Qualcomm)
• 11.5 Disturbance Free Read Scheme for STT MRAM/SPRAM (Hitachi, Tohoku Univ.)

12.0 Write Current and Thermal Stability in STT MRAM

• 12.1 Write Current Density and Temperature in (Ga,Mn)As MTJs (IMEC)
• 12.2 Low Write Current and High Thermal Stability in CoFeB/Ru MTJ (AIST)
• 12.3 Switching of MgO MTJ STT MRAM with CoFeB/Ta/NiFE free layers (Qualcomm)
• 12.4 Effect of 150 C Temperature on SPRAM with SyF Layer (Hitachi and Tohoku U.)
• 12.5 Switching Probability of CoFeB/MgO at High Bias V and H (IBM-MagIC)

13.0 Domain Wall Spin Polarized MRAM Cell for Embedded Applications (NEC)

• 13.1 Critical Current of Perpendicular Domain Wall Motion and Wire Dimension (NEC)
• 13.2 Domain Wall Motion and Thermal Stability of Co/Ni Strips (NEC)
• 13.3 Perpendicular Domain Wall Spin-Polarized MRAM (NEC)
• 13.4 Current with Perpendicular Magnetic Anisotropy and Domain Wall Motion (NEC)
• 13.5 In-Plane Domain Wall Spin Polarized MRAM (NEC)

14.0 MRAM with Spin Transfer Write and Perpendicular Anisotropy

• 14.1 Comparison of In-Plane vs. Perpendicular STT MRAM Technology
• 14.2 Properties of Perpendicular Magnetized MnGa Epi Films (Tohoku U.)
• 14.3 Switching Study for In-Plane and Perpendicular STT MRAM (Qualcomm)
• 14.4 Combined Perpendicular Magnetic Technology and Spin Transfer Switching(Toshiba)
• 14.5 Spin transfer MRAM using Perpendicular Anisotropy (Siemens, Altis)

15.0 Simulation and Modeling of Spin Write MRAMs

• 15.1 SPICE Model of Two Terminal Device Representing STT MRAM (U of Minnesota)
• 15.2 Numerical Simulation of Spin Field Effect Transistors (Intel, Purdue U.)
• 15.3 Cell Structure Design Simulation for STT MRAM CAM/TCAM (Rensselaer Polytech)
• 15.4 Modeling and Analysis of an STT MRAM (Intel)
• 15.5 MTJ Circuit Model for STT MRAM Spin Dynamics (Hitachi, Tohoku University)
• 15.6 Simulation of MRAM Magnetic Energy Barrier with Synthetic Ferrimagnets (KoreaU)
• 15.7 Design Method to Improve STT MRAM Yield Loss due to Process Variation (PurdueU)
• 15.8 Modeling Failure Probability and Statistical Design for STT MRAM (Purdue Univ.)
• 15.9 Model of MTJ Integrated Above CMOS Circuitry in MRAM or MFPGA (IEF, CNRS)
• 15.10 Macromodel of Spin Programmed MRAM Showing Insulator Defects
• 15.11 Simulations to Investigate Dynamics of Switching in STT MTJs (Qualcomm)
• 15.12 Analysis of Effect of Process Variation on yield of STT MRAM (Purdue U.)
• 15.13 Probability Distribution Describing Eff. Energy in Spin Torque Systems (U.Alabama)
• 15.14 Veralog-A Behavioral Model for MRAM Spin Valve (Oregon State U. )
• 15.15 Thermal Fluctuations in Write Error Probability of STT-MRAM (Renesas)
• 15.16 Model and Design Methodology for Failures Due to Process Variations (Purdue U.)

16.0 Test, Yield and Reliability Issues for Spin Program MRAM

• 16.1 Thermal Stability of STT MRAM (Grandis)
• 16.2 Write Margin of 90 nm STT MRAM Technology
• 16.3 High Temperature Operation of STT-MRAM (Qualcomm)
• 16.4 Magnetic Force Microscopy for PSV Stability with Perpendicular Anisotropy (NUS)
• 16.5 MRAM Test Method for Write Disturbance Faults in BIST (Nat. Tsing Hua U.)
• 16.6 Yield Improvement by Circuit Design Paradigm (Purdue Univ.)
• 16.7 TDDB Characteristics of 1 nm Thick MgO Barrier for a STT-MRAM (Fujitsu)
• 16.8 Field/Bias Dependence of High Frequency Magnetic Noise on MgO MTJ (IBM-MagIC)
• 16.9 Dependence of TDDV with Voltage Pulsewidth on MgO MTJ (Crocus & Labs)
• 16.10 Magnetic Shielding for MRAM Devices

17.0 Thermal Assisted Write in MRAMs

• 17.1 Writing TAS MRAM FeMn Layers in 50 ns at below 10mW/um3 (Crocus)
• 17.2 Modeling Thermal Assisted Switching Spin MRAM Technology (Crocus)
• 17.3 TAS-MRAM using Pre-Charged Sense Amps for Embedded Memory (IEF, CNRS)
• 17.4 STT MRAM with Thermal Assist Mechanism ( Seagate Technology)
• 17.5 Programming of Thermal Assisted STT-RAM (Seagate)
• 17.6 Characterization of Thermal Assisted MRAM Cell Switching (Spintec,CEA,CNRS)
• 17.7 Thermal Programming Above the Blocking Temperature (Crocus)
• 17.8 Thermal Assisted Switching MRAM (TAS-MRAM) Element in FPGA (INESC-ID)
• 17.9 Magnetization Reversal of TbFe Film During Heat Assisted Write (Kyushu U.)

18.0 Effect of Magnetic Element Shape on STT MRAMs

• 18.1 Elongated Pac-Man Spin Valve for Fast Spin Polarized Current Switching

19.0 Circular Ring Element MRAMS

• 19.1 Annular STT MRAM (New York University)
• 19.2 Bit Storage by 360 Domain Walls in Magnetic Nanorings(NJ Inst Tech, MCT,NASA)

20.0 STT MRAM Circuit Techniques

• 20.1 Negative Resistance Read and Write Schemes for STT-MRAM (Fujitsu,U of Toronto)
• 20.2 Reference Schemes for a 64-Mb MRAM Using Perpendicular TMR (Toshiba)

21.0 Logic and 3D Circuits Using MRAM

• 21.1 MRAM CAM Cell Design (U. of Wisconsin)
• 21.2 MRAM-Based FPGA Design Tape Out (Menta SAS, Crocus, Montpellier Lab)
• 21.3 FPGA Circuit Based on Thermally Assisted Switching MRAM (LIRMM)
• 21.4 CMOS/MTJ Integration in Logic Components (Crocus, Spintec, CEA/SNRS, INAC)
• 21.5 Magnetic Flip-Flop Primitive Cell for Logic Design Libraries (NEC)
• 21.6 Programmable ALU Storing Configuration Bits in MRAM (Univ. of Lisbon)
• 21.7 MRAM-based Run-Time System on Programmable Chip(STMicro & U. of Paris Sud)
• 21.8 Non-Volatile Magnetic Flip Flop for SoC
• 21.9 3D Reconfigurable Logic Block Using SPRAM
• 21.10 3D Stacking of MRAMs on Chip Multiprocessors
• 21.11 32-Mb MRAM Macro for Embedding in SoC.
• 21.12 Ternary CAM Using 6T and 2 MRAM Storage
• 21.13 Non-Volatile Register Based on Hybrid MRAM and CMOS Logic(IEF and CNRS)
• 21.14 FPGA Using Thermally Assisted MRAM (U. of Montpellier)
• 21.15 ALU with Spintronic MRAM (Hitachi and Tohoku U.)

22.0 MTJ MRAM Materials and Device Research Issues

• 22.1 Nano-Spiral Inductors for Use in MRAMs (Intel, Purdue U. )
• 22.2 Spin-Flop Tunnel Junctions (IBM, Royal Institute of Technology Stockholm)
• 22.3 Reconfigurability of Spintronics-Based MOSFET (Toshiba)
• 22.4 Magnetization in Perpendicularly Magnetized CoFeB Film(Tohoku U.,U.of Gottingen)
• 22.5 MRAM Using Ferroelectric Layer for 90 Degree Switching (Tsinghua Univ.)
• 22.6 Magnetic Dead Layer in Amorphous CoFeB used as Free Layer in MTJ (Korea U.)
• 22.7 Finding Magnetic Field from Magnetic Clad Line(Nat. Taiwan U/N.Taiwan Ocean U)
• 22.8 MgO Dep. with Substrate Bias in CoFeB/MgO/CoFeB MTJ (KIST, Samsung, KAIST)
• 22.9 STT Switching in Multilayered Co/Cu 10 nm Nanowires (U. of Minnesota)
• 22.10 Magnetic Coupled Spin Torque Devices (Stanford)
• 22.11 Current Induced Switching with Composite Free Layer (U. of Minnesota, Yadav)
• 22.12 Conductive Changes in Trace Magnetism in Nanotubes (Rensselaer)
• 22.13 Stacking MRAM as an Alternative to Embedding (Penn State U.)

23.0 MRAM Vendors and Developers

• 23.1 Avalanche Technology
• 23.2 Crocus
• 23.3 Freescale / Everspin
• 23.4 Fujitsu
• 23.5 Grandis STT-RAM
• 23.6 Hitachi
• 23.7 Honeywell
• 23.8 Hynix
• 23.9 IBM
  • 23 .9.1 IBM, Royal Institute of Technology Stockholm
  • 23.9.2 IBM and MagIC Technologies
  • 23.9.3 IBM RaceTrack Memory
• 23.10 Intel
• 23.11 MagSil
• 23.12 Micromem
• 23.13 NEC
  • 23.13.1 Magnetic Flip-Flop Primitive Cell for Logic Design Libraries (NEC)
  • 23.13.2 NEC Domain Wall Spin Polarized MRAM
  • 23.13.3 MRAM in SoC (NEC)
  • 23.13.3 NEC Toggle Mode MRAM
  • 23.13.4 2T1MJT Cell for Write Current Control (NEC)
• 23.14 Qualcomm
• 23.15 Renesas
• 23.16 Samsung
• 23.17 Seagate
• 23.18 STMicroelectronics
• 23.19 Toshiba
• 23.20 TSMC

Bibliography

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