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A Memory Strategies Focus Report on MRAM - New Report for 2010

Magnetic RAM (MRAM) Product, Technology, R&D October 2011
(STT-MRAM, Field Write MRAM, Merged CMOS Logic, Multi-Bit, Test, Applications, Roadmaps, Reliability, Modeling, Architecture)

This report tracks MRAM technology, development, and product. One vendor is in production with a field write MTJ MRAM and another vendor is projecting being in production within a year also with a field write type of MRAM. Some MRAM wafer fabrication areas are coming up. Several MRAM development alliances and acquisitions have been announced recently resulting in the field of developers shrinking and patent ownership becoming concentrated. The STT-MRAM technology continues in active development as various issues are addressed. The source degeneration - current asymmetry issue appears to be satisfactorily addressed. Much effort has been directed at thermal stability issues in the past year. MRAMs with perpendicular anisotropy show promise for scaled MRAM and many studies have been done. Simulation and modeling effort continues to add to the understanding of MRAM as do the many test, yield and reliability studies. Support circuits for MRAM arrays are in development. Many materials and device research issues are being addressed. A significant amount of development work is ongoing on integrated MRAM and logic which is also covered in this report.

130+ pages.

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Table of Contents - Magnetic RAM Product, Technology, R&D October 2011

1.0 Overview of Current MRAM Application, Product, Development and Technology

2.0 Current and Projected Magnetic RAM Applications

• 2.1 Overview of Propective MRAM Applications
• 2.2 Replacement for Existing Memory Types - SRAM
  • 2.2.1 Embedded SRAM Replacement in Parallel Many Core Computing Chips(Purdue U.)
  • 2.2.2 Standalone SRAM Replacement
  • 2.2.3 Hybrid SRAM-MRAM Design for L1 Cache (Xi'an Jiaotong U.)
  • 2.2.4 Cache in Graphics Processing Units with Small Number of Writes
  • 2.2.5 DRAM Replacement Applications
  • 2.2.6 NOR Flash Replacement
  • 2.2.7 NAND Flash Replacement Applications
  • 2.2.8 MRAM for Soft Error Protection in IC System Storage Structures (Penn State Univ.)
• 2.3 Automotive Applications
• 2.4 Industrial Applications
  • 2.4.1 Serial Peripheral Interface Applications
  • 2.4.2 Small Industrial Applications
• 2.5 Consumer Applications
  • 2.5.1 Mobile Phone MRAM Applications
  • 2.5.2 Low Power Mobile Applications
• 2.6 Aerospace Applications
  • 2.6.1 Flight Control Computers in Airplanes
• 2.7 Space and Military Applications

3.0 MRAM Production Roadmaps

• 3.1 Announced Production and Prototyping for Various MRAM Developers

4.0 Recent MRAM Production, Development, Manufacturing and Financial Announcements

• 4.1 Overview of Recent MRAM Alliances
• 4.2 Crocus MRAM (CEA, IBM, TowerJazz, Rusnano, NXP IP)
• 4.3 EverSpin
  • 4.3.1 EverSpin Spin-Torque MRAM
  • 4.3.2 EverSpin Field Write MRAM
• 4.4 Hitachi Spin Transfer Torque MRAM (SPRAM)
• 4.5 Hynix - Toshiba
• 4.6 NEC/Renesas MRAM
• 4.7 Samsung - Grandis

5.0 Spin Transfer Torque (STT) MRAM Device, Design, and Process

• 5.1 Integration of 28 nm MTJ for 16-Gb MRAM (Samsung)
• 5.2 Low Energy MTJ for Fast STT-MRAM (Hitachi, Singulus, U. of Calif. U. of Minn.)
• 5.3 Sub-30 nm STT MRAM with On-Axis MTJ (Samsung)
• 5.4 Read and Restore for G-bit STT MRAM to Replace DDR SDRAM (Hitachi)
• 5.5 Spin Injection from thin Fe film into silicon (Naval Research Lab.)
• 5.6 Spin-Transfer Precessional Switching with Sub-ns Current Pulse(INAC/SPINTEC,CEA)
• 5.7 Improving Density of STT MRAM with Current Threshold Variability (Rensselaer)
• 5.8 32-Mb 2T1R STT-MRAM "SPRAM" with 300 uA/cell Write (Hitachi, Tohoku U.)

6.0 Multiple Layer Stacked STT- MRAM

• 6.1 3-D MRAM Using Various AC Resonant Frequencies and Multiple Layers(Vienna U.Tech)
• 6.2 Multi-Level Cell STT-MRAM with Series Connected MTJs (Hitachi, Tohoku U.)
• 6.3 STT Switching in Multilayered Co/Cu 10 nm Nanowires (U. of Minnesota)

7.0 Source Degeneration Effect and Current Asymmetry Issue in STT MRAM

• 7.1 Balancing Transistor Drive Asymmetry and MTJ Source Degeneration Effect(Seagate)
• 7.2 STT-MRAM with Top Pinned 1T1M Cell For Write Current Asymmetry Issue (Fujitsu)
• 7.3 SAF reference layer in MTJ to Reduce Asymmetry Causing Reversal (Crocus, Spintec)
• 7.4 Theory of Switching Current Asymmetry of MTJs in STT MRAMs (Qualcomm)
• 7.5 45 nm Embedded STT MRAM Solving Source Degeneration Issue(TSMC, Qualcomm)
• 7.6 Disturbance Free Read Scheme for STT MRAM/SPRAM (Hitachi, Tohoku Univ.)

8.0 Thermal Stability Issues in STT MRAM

• 8.1 Stepped Structure for Calibrated Retention in CoFeB/MgO p-MTJ (Hitachi,Tohoku U)
• 8.2 Thickness of MgO vs. Stack Temperature During MTJ Programming (Khon Kaen U.)
• 8.3 Write Current Density and Temperature in (Ga,Mn)As MTJs (IMEC)
• 8.4 Low Write Current and High Thermal Stability in CoFeB/Ru MTJ (AIST)
• 8.5 Switching of MgO MTJ STT MRAM with CoFeB/Ta/NiFE free layers (Qualcomm)
• 8.6 Effect of 150 C Temperature on SPRAM with SyF Layer (Hitachi and Tohoku U.)
• 8.7 Switching Probability of CoFeB/MgO at High Bias V and H (IBM-MagIC)

9.0 Domain Wall Spin Polarized MRAM Cells

• 9.1 Domain Wall and STT-MRAM in Parallel Many Core Computing Chips(Purdue U.)
• 9.2 16-Kbit Spin-CAM Using Domain Wall MRAM Technology (NEC, Tohoku Univ.)
• 9.3 Critical Current of Perpendicular Domain Wall Motion and Wire Dimension (NEC)
• 9.4 Domain Wall Motion and Thermal Stability of Co/Ni Strips (NEC)
• 9.5 Perpendicular Domain Wall Spin-Polarized MRAM (NEC)

10.0 Three Terminal STT-MRAM Cells

• 10.1 Dual Pillar STT-MRAM with Tilted Magnetic Anisotropy (Purdue University)
• 10.2 Three Terminal Dual Pillar STT-MRAM Cell for Fast Applications (Intel, Purdue U.)
• 10.3 3-Terminal Spin-Torque MRAM with Separated Read&Write Operations (IBM-MagIC)
• 10.4 Combination Spin-Torque and Field Programmable MRAM (Hitachi)

11.0 MRAM with Spin Transfer Write and Perpendicular Anisotropy

• 11.1 Study of Device Properties of PMA Junctions (IBM, MagIC)
• 11.2 MTJ Technology using Perpendicular Anisotropy with Material Advances (Grandis)
• 11.3 Spin Torque Effect on Current and Speed of Perpendicular MRAM (H.K. Inst.Tech)
• 11.4 Spin Torque Perpendicular 90 nm MRAM without Anomalous Switching (IBM-MagIC)
• 11.5 Analysis of Perpendicular STT MRAM with 0.7V Bipolar Switching (New York U.)
• 11.6 Comparison of In-Plane vs. Perpendicular STT MRAM Technology (Grandis)
• 11.7 Magnetization in Perpendicularly Magnetized CoFeB Film (Tohoku U.,U.of Gottingen)
• 11.8 Properties of Perpendicular Magnetized MnGa Epi Films (Tohoku U.)
• 11.9 Switching Study for In-Plane and Perpendicular STT MRAM (Qualcomm)

12.0 Simulation and Modeling of Spin Write MRAMs

• 12.1 Modeling an Fe-MgO-Fe MTJ MRAM (Karunya University)
• 12.2 Energy Theory of MRAM Switching Speed (NVE Corp.)
• 12.3 Design Technique to Reduce Variation Induced Failures in STT-MRAM(Purdue U.)
• 12.4 SPICE Model of Two Terminal Device Representing STT MRAM (U of Minnesota)
• 12.5 Cell Structure Design Simulation for STT MRAM CAM/TCAM(Rensselaer Polytech)
• 12.6 Modeling and Analysis of an STT MRAM (Intel)
• 12.7 MTJ Circuit Model for STT MRAM Spin Dynamics (Hitachi, Tohoku University)
• 12.8 Simulation of MRAM Magnetic Energy Barrier using Synthetic Ferromagnets(Korea U.)
• 12.9 Design Method to Improve STT MRAM Yield Loss due to Process Variation (Purdue U)
• 12.10 Modeling Failure Probability and Statistical Design for STT MRAM (Purdue Univ.)
• 12.11 Model of MTJ Integrated Above CMOS Circuitry in MRAM or MFPGA(IEF, CNRS)
• 12.12 Macromodel of Spin Programmed MRAM Showing Insulator Defects
• 12.13 Simulations to Investigate Dynamics of Switching in STT MTJs (Qualcomm)
• 12.14 Analysis of Effect of Process Variation on Yield of STT MRAM (Purdue U.)

13.0 Test, Yield and Reliability Issues for STT- MRAM

• 13.1 Switching Probability Distribution of Spin Torque Switching in MgO MTJ (AIST)
• 13.2 MRAM use for Soft Error Protection in IC System Storage Structures (Penn State U.)
• 13.3 Model of Dielectric BD Induced STT-MRAM Performance Degradation (Purdue U.)
• 13.4 Wafer Level Testing of 4-Kbit Perpendicular Anisotropy STT-MRAM (IBM-MagIC)
• 13.5 Methods for Low Power Embedded STT-MRAM with Process Variation (Purdue U.)
• 13.6 Parameter Characterization of a MgO MTJ for RA, EW and Jc (Univ. of Calif. LA)
• 13.7 Write Margin of 90 nm STT MRAM Technology (IBM, MagIC)
• 13.8 Thermal Stability of STT MRAM (Grandis)
• 13.9 High Temperature Operation of STT-MRAM (Qualcomm)
• 13.10 Magnetic Force Microscopy Shows PSV Stability with Perpendicular Anisotropy(NUS)
• 13.11 MRAM Test Method for Write Disturbance Faults in BIST (Nat. Tsing Hua U.)
• 13.12 Yield Improvement by Circuit Design Paradigm (Purdue Univ.)
• 13.13 TDDB Characteristics of 1 nm Thick MgO Barrier for a STT-MRAM (Fujitsu)
• 13.14 Field/Bias Dependence of High Frequency Magnetic Noise on MgO MTJ (IBM-MagIC)

14.0 Thermal Assisted Write in MRAMs

• 14.1 Writing TAS MRAM FeMn Layers in 50 ns at below 10mW/um3 (Crocus)
• 14.2 TAS-MRAM using Pre-Charged Sense Amps for Embedded Memory (IEF, CNRS)
• 14.3 STT MRAM with Thermal Assist Mechanism ( Seagate Technology)
• 14.4 Modeling Thermal Assisted Switching Spin MRAM Technology (Crocus)
• 14.5 Programming of Thermal Assisted STT-RAM (Seagate)
• 14.6 Characterization of Thermal Assisted MRAM Cell Switching (Spintec,CEA,CNRS)
• 14.7 Thermal Programming Above the Blocking Temperature (Crocus)
• 14.8 Thermal Assisted Switching MRAM (TAS-MRAM) Element in FPGA (INESC-ID)

15.0 Circular Ring Element MRAMS

• 15.1 Annular STT MRAM (New York University)
• 15.2 Bit Storage by 360 Domain Walls in Magnetic Nanorings( NJ Inst. of Tech, MCT,NASA)
• 15.3 Pac-Man Spin Valve for Fast Spin Polarized Current Switching(Western Dig., Seagate)

16.0 STT MRAM Circuit Techniques

• 16.1 Two Terminal Switch for Crossbar Array (Hanyang Univ., Korea Basic Sci. Inst.)
• 16.2 45 nm 1-Mb Embedded STT-MRAM Circuitry (Qualcomm)
• 16.3 Designs for Multi-Level MRAMs with 3-Bits/Cell (Durham University)
• 16.4 Sensing Scheme for STT-MRAM with High Signal Margin (Tohoku Univ.)
• 16.5 STT-MRAM Sense Circuit Using Source Degeneration & Balanced Reference(Yonsei U)
• 16.6 Negative Resistance Read and Write Schemes for STT-MRAM (Fujitsu, U. of Toronto)
• 16.7 Reference Schemes for a 64-Mb MRAM Using Perpendicular TMR (Toshiba)

17.0 Integrated Logic, Embedded MRAM and 3D MRAM Circuits

• 17.1 MRAM and Magnetic Logic Unit Technology (IBM and Crocus)
• 17.2 Magnetic Logic Unit Technology: NOR, NAND, XOR (Crocus)
• 17.3 16-Kbit Spin-CAM Using Domain Wall MRAM Technology (NEC, Tohoku Univ.)
• 17.4 Modeling a Hybrid MRAM-Processor Stack (Penn State Univ.)
• 17.5 Methods for Low Power Embedded STT-MRAM with Process Variation (Purdue U.)
• 17.6 STT-MRAM Embedded in SoC for Mobile Applications (Qualcomm)
• 17.7 Reconfigurable Logic Using Spin Field Effect Transistors (Intel, Purdue U.)
• 17.8 MRAM CAM Cell Design (U. of Wisconsin)
• 17.9 MRAM-Based FPGA Design Tape Out (Menta SAS, Crocus, Montpellier Lab)
• 17.10 FPGA Circuit Based on Thermally Assisted Switching MRAM (LIRMM)
• 17.11 CMOS/MTJ Integration in Logic Components (Crocus, Spintec, CEA/SNRS, INAC)
• 17.12 Magnetic Flip-Flop Primitive Cell for Logic Design Libraries (NEC)
• 17.13 Programmable ALU Storing Configuration Bits in MRAM (Univ. of Lisbon)
• 17.14 MRAM-based Run-Time System on Programmable Chip(STMicro & U. of Paris Sud)
• 17.15 Non-Volatile Magnetic Flip Flop for SoC (NEC)
• 17.16 3D Stacking of MRAMs on Chip Multiprocessors (Penn. State U.)
• 17.17 32-Mb MRAM Macro for Embedding in SoC. (NEC)

18.0 Field Switching MTJ MRAM Device Technology

• 18.1 Field Programmed High Capacity Perpendicular MRAM (Pusan National U)
• 18.2 16-Mb Field Switching MRAM in 180 nm Technology (Everspin)

19.0 Methods for Lowering MTJ MRAM Write Current in Field Switching MRAMs

• 19.1 Nano-Spiral Inductors Decrease Current to Field Written MRAMs (Intel, Purdue U. )
• 19.2 Effect of MTJ Edge Deformation on Switching Current (NEC)
• 19.3 Diamond Shaped Field Programmed MRAM Elements (U. of Alabama)
• 19.4 2T1MJT Cell for Write Current Control (NEC)

20.0 Embedded Field Programmed MRAM in Conventional CMOS Logic

• 20.1 MRAM L2 Cache Stacked on Multiprocessor (Penn. State U.)
• 20.2 Embedded MRAM to Replace SRAM in SoC (NEC)

21.0 Test, Reliability and Modeling in MTJ Field Switching MRAMs

• 21.1 Test Method Using BIST for Detecting Write Disturbance Faults (Skymedi Corp)
• 21.2 Verilog-A Model for Toggle Mode MRAM (Oregon State Univ.)
• 21.3 Formula for Saturation Field for Toggle Mode MRAM (AIC University)
• 21.4 SPICE Model of Field Programmable MRAM Circuit (Rochester Inst. of Tech)

22.0 MTJ MRAM Materials and Device Research Issues

• 22.1 Using Magnetic Fringing Fields to Set the State of an MTJ (Univ. of Notre Dame)
• 22.2 Process for a Perpendicular Spin MRAM Stack (NYU,Singulua, Spin-Transfer Technology)
• 22.3 Strain Engineering to Improve STT-MRAM Performance (LEAP)
• 22.4 Potential of Doped/Undoped Graphene in an MRAM Element (Chinese Acad. of Sci.)
• 22.5 Precessional Effect on Magnetic Switching (U. S. Carolina, Inst Mag. Ukraine, NVE)
• 22.6 Spin Valve-Like Signal of antiferromagnet and non-magnetic metal (Hitachi Cambridge)
• 22.7 Spin-Flop Tunnel Junctions (IBM, Royal Institute of Technology Stockholm)
• 22.8 Reconfigurability of Spintronics-Based MOSFET (Toshiba)
• 22.9 MRAM Using Ferroelectric Layer for 90 Degree Switching (Tsinghua Univ.)
• 22.10 Magnetic Dead Layer in Amorphous CoFeB used as Free Layer in MTJ (Korea U.)
• 22.11 Finding Magnetic Field from Magnetic Clad Line(Nat. Taiwan U/N.Taiwan Ocean U)
• 22.12 MgO Dep. with Substrate Bias in CoFeB/MgO/CoFeB MTJ (KIST, Samsung, KAIST)

23.0 MRAM Vendors and Developers

• 23.1 Avalanche Technology
• 23.2 Crocus
  • 23.2.1 Crocus and Rusnano
  • 23.2.2 Crocus and TowerJazz
  • 23.2.3 Crocus General
• 23.3 Freescale / Everspin
• 23.4 Fujitsu
• 23.5 Hitachi
• 23.6 Honeywell
• 23.7 Hynix and Toshiba
  • 23.7.1 Hynix and Toshiba
  • 23.7.2 Hynix
  • 23.7.3 Toshiba
• 23.8 IBM
  • 23.8.1 IBM and Crocus
  • 23.8.2 IBM and MagIC
  • 23.8.3 IBM and Royal Institute of Technology Stockholm
• 23.9 Intel
• 23.10 MagSil
• 23.11 NEC
• 23.12 NVE
• 23.13 Qualcomm
  • 23.13.1 Qualcom
  • 23.13.2 Qualcomm and TSMC
• 23.14 Samsung (including Grandis)
  • 23.14.1 Samsung and Grandis
  • 23.14.2 Samsung
  • 23.14.3 Grandis STT-RAM
• 23.15 Seagate
• 23.16 Spin Transfer Technology
• 23.17 STMicroelectronics

Bibliography

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