MEMORY STRATEGIES INTERNATIONAL Semiconductor Memory Services
| Home | Reports | Seminars | Consulting | Contact Us | About Us | Site Map | Links |

Contents | Purchase

A Memory Strategies Focus Report on MRAM - New Report for 2009

Magnetic RAM (MRAM) Product, Development & Technology, March 2009
(STT-MRAM, Toggle/Field Write MRAM, Hybrid MTJ-CMOS Logic, Test Applications, Roadmaps, Reliability, Modeling, Multi-Bit, Architecture)

MRAM Product, Development & Technology, March 2009, is now available. This report discusses applications of MRAMs in production today along with projected production roadmaps for MRAMs  from various companies. Several companies have continued to work on variations of the field programmable MTJ MRAM.  One has introduced a product line of standalone MRAM components.  Another has shown low current field programmable MRAM macro's for embedding in SoC. There has been work on multiple-bit-per-cell field write MRAMs.  Recent development  has also focused  on the Spin Torque Transfer MRAMs (STT-MRAMs).  Efforts on spin-torque-transfer MRAM technology with perpendicular magnetic elements appear to be nearing production. Numerous examples of MTJ elements used in various CMOS logic circuits have been discussed.   A 64Mb STT-MRAM in 90 nm technology is considered currently feasible.  STT-MRAM is generally expected in production in the 2010 timeframe.  Multiple studies of simulations and modeling of MRAM process technology, and of reliability and test of MRAMs are discussed. Vendors and developers of MRAMs are listed along with their respective technologies.  Pages: 90+

Overview | Purchase

Table of Contents - Magnetic RAM Product, Development & Technology, March 2009

Table of Contents

1.0 Overview of Current MRAM Product, Development and Technology

2.0 Current Magnetic RAM Applications

• 2.1 Overview of Propective MRAM Applications
• 2.2 Automotive MRAM Applications
  • 2.2.1 Automotive Airbags
  • 2.2.2 Automotive Data Logging and Configuration Storage.
  • 2.2.3 Automotive Crash Recorders:
  • 2.2.4 Automotive Sensor Applications:
• 2.3 Industrial Applications
  • 2.3.1 Industrial Touch-Screen Application
• 2.4 Consumer Applications
  • 2.4.1 Portable Multimedia Applications
  • 2.4.2 Gaming Machines:
  • 2.4.3 Mobile Phone MRAM Applications
  • 2.4.4 Entertainment Systems:
• 2.5 Encryption for Security Systems:
• 2.6 Rad Hard Military Applications
• 2.7 Space Applications
• 2.8 RFID Applications
• 2.9 Networking and Server Applications
• 2.10 Embedded MRAM Macro Applications
• 2.11 FPGA Development Card

3.0 MRAM Production Roadmap

• 3.1 Crocus MRAM IP
• 3.2 Freescale/ EverSpin Field Write MRAM
• 3.3 Grandis STT-RAM
• 3.4 Hitachi Spin-Torque Transfer MRAM
• 3.5 IBM and TKD Spin Transfer Write MRAM
• 3.6 Magsil Proprietary MRAM Technology
• 3.7 MicroMem Hall Effect MRAM and Sensor
• 3.8 Renesas Embedded MRAM:
• 3.9 Samsung and Hynix Spin Transfer Torque MRAM
• 3.10 Toshiba Perpendicular Spin Transfer Torque MRAM

4.0 Overview of Spintronic Theory

• 4.1 Field Programmed MRAM Theory
• 4.2 Spin Transport and Spin Programmable Device Theory.
  • 4.2.1 Overview of Spin Transport Mechanism Theory
  • 4.2.2 Theory of Lateral Spin Valves /Spin Accumulation MRAMs (U.S. Naval Res. Lab)
• 4.3 Trends in Field Write (F-MRAM) and Spin Write MRAMs (S-MRAM)

5.0 Field Switching MTJ MRAM

• 5.1 Thermal Assisted Field MRAM Switching
  • 5.1.1 Magnetization Reversal of TbFe Film During Heat Assisted Write (Kyushu U.)
  • 5.1.2 Influence of Pinning Field Dispersion of Coercivity (NVE)
• 5.2 Field Switching of MTJ MRAM using Toggle Mode
  • 5.2.1 Reducing the Programming Field Strength for a Toggle Mode MRAM (NEC)
  • 5.2.2 Variations of Orientation of the Free layer in Toggle Mode MRAMs (NEC)
  • 5.2.3 Study of Toggle Mode MRAM Dynamic Switching Behavior(Grandis, U. of Alabama)
• 5.3 Methods for Lowering MTJ MRAM Write Current in Field Switching MRAMs
  • 5.3.1 2T1MJT Cell for Write Current Control (NEC)
• 5.4 Embedded Field Programmed MRAM in Conventional CMOS
  • 5.4.1 Magnetic Primitive Cell for SoC Libraries Using MRAM/CMOS Process (NEC)
  • 5.4.2 Dual Port 5T2MTJ Cell in SoC MRAM Technology (NEC)
• 5.5 Test, Reliability and Modeling in MTJ Field Switching MRAMs
  • 5.5.1 Technique for Evaluating Write Disturb Robustness in Toggle Mode MRAMs (NEC)
  • 5.5.2 Using Systematic Tools for MRAM Analysis (Nat. Tsing Hua University)
  • 5.5.3 Write Disturb Faulting Modeling for Toggle Mode MRAM (Nat. Tsing Hua U.)
  • 5.5.4 Correlation Study Between Electrical and Magnetic Properties of MTJ (Korea SEF)
  • 5.5.5 Effects of Weak Magnetostatic Interactions Among Adjacent MRAM Cells (Husko)

6.0 Perpendicular MTJ MRAMS

• 6.1 MTJ Elements With a MgO Barrier for Perpendicular MRAM ( U. of Tokyo)
• 6.2 Double Barrier Layer Perpendicular MTJ Structure (Taiwan SPIN Center)
• 6.3 Magnetization Reversal for Perpendicular MRAM (Tokyo Inst. of Tech.)

7.0 Multiple Bit-Per-Cell Field Program MRAMs

• 7.1 Four-Bit MRAM Cell using Two Stacked MRAM Cells (MagLabs)
• 7.2 Four State MRAM Using Easy Axes Cubic Anisotropy in {110} Direction (Hokkaido U.)

8.0 Field Program MRAM Architectural Innovations

• 8.1 Shared Write Select Transistor Macro Based on 2T1MTJ Cell (NEC)
• 8.2 1T1MTJ Bit-Line Separated and Half Pitch Shifted MRAM Cell (NEC)
• 8.3 5T2MTJ Cell for GHz Access Time (NEC)

9.0 Spin Transfer Switching MRAM

• 9.1 Overview of Electron Spin Torque Switching
• 9.2 Spin Transfer Torque MRAM (Hitachi)
• 9.3 Spin-Torque Transfer (STT) RAM (Grandis)
• 9.4 Current Induced MRAM Switching with a Composite Free Layer (U. of Minnesota, Yadav)
• 9.5 Spin Torque Switching with Various Thickness of MgO (Taiwan Spin, N. Yunlin U.)

10.0 Domain Wall Spin Polarized MRAM Cell for Embedded Applications (NEC)

• 10.1 Theory of Domain Wall Spin Polarized MRAM (NEC)
• 10.2 Circuits for MRAM Cells Using Domain Wall Spin Polarized Switching (NEC)
• 10.3 Current with Perpendicular Magnetic Anisotropy and Domain Wall Motion (NEC)

11.0 MRAM with Spin Transfer Write and Perpendicular Anisotropy

• 11.1 Combined Perpendicular Magnetic Technology and Spin Transfer Switching(Toshiba)
• 11.2 Spin transfer MRAM using Perpendicular Anisotropy (Qimonda, Siemens, Altis)
• 11.3 GMR MRAM Using Perpendicular Magnetization and Spin Injection Write(AIST)

12.0 Simulation and Modeling of Spin Write MRAMs

• 12.1 Analysis of Effect of Process Variation on yield of STT MRAM (Purdue U.)
• 12.2 Probability Distribution Describing Eff. Energy in Spin Torque Systems(U. of Alabama)
• 12.3 Thermal Fluctuations in Write Error Probability of STT-MRAM (Renesas)
• 12.4 Verolog-A Behavioral Model for MRAM Spin Valve (Oregon State U. )
• 12.5 Model and Design Methodology for Failures Due to Process Variations (Purdue U.)
• 12.6 Modeling STT MRAM Cells (Purdue U.)
• 12.7 Simulation of Spin Torque Transfer MRAMs (Purdue U.)
• 12.8 Simulation Study of Physical Factors Involved in Switching Spin Valves

13.0 Test and Reliability Issues for Spin Program MRAM

• 13.1 Dependence of TDDV with Voltage Pulsewidth on MgO MTJ (Crocus & Labs)
• 13.2 Magnetic Shielding for MRAM Devices (U. of Wisconsin)
• 13.3 Reducing Switching Current Variation for Spin Injection MRAM (Toshiba)
• 13.4 Oxidizing MTJ Free Layer to Reduce Switching Field Variation (Mitsubishi, Renesas)
• 13.5 Reliability of MgO vs. AlOx Tunneling Barriers in ST MTJ MRAM (Toshiba)

14.0 Circular Ring Element MRAMS

• 14.1 Effect of Gilbert Damping on Magnetic Reversal of a Ring-Shaped PSV (NUS)
• 14.2 Nanoring MRAMs (Chinese Academy of Science)

15.0 Hall Effect MRAMs (Micromem)

16.0 Logic Circuits Using MRAM

• 16.1 3D Reconfigurable Logic Block Using SPRAM
• 16.2 3D Stacking of MRAMs on Chip Multiprocessors
• 16.3 32-Mb MRAM Macro for Embedding in SoC.
• 16.4 Ternary CAM Using 6T and 2 MRAM Storage
• 16.5 Non-Volatile Register Based on Hybrid MRAM and CMOS Logic(IEF and CNRS)
• 16.6 MRAM Based FLIP-FLOP in CMOS Technology
• 16.7 FPGA Using Thermally Assisted MRAM (U. of Montpellier)
• 16.8 ALU with Spintronic MRAM (Hitachi and Tohoku U.)

17.0 MTJ MRAM Materials and Device Research Issues

• 17.1 Magnetic Coupled Spin Torque Devices
• 17.2 Conductive Changes in Trace Magnetism in Nanotubes
• 17.3 Stacking MRAM as an Alternative to Embedding
• 17.3 Effect on MR of Various Capping Materials used on MTJ's (ERSO/ITRI)

18.0 MRAM Vendors and Developers

• 18.1 Crocus
• 18.2 Freescale / Everspin
  • 18.2.1 Freescale/ Everspin Production MTJ Toggle-Mode MRAM Devices
  • 18.2.2 Freescale Technology Development
• 18.3 Altis/Qimonda
• 18.4 Grandis STT-RAM
• 18.5 Hitachi
• 18.6 Honeywell
• 18.7 Hynix
• 18.8 IBM
  • 18.8.1 IBM and MagIC Technologies
  • 18.8.2 IBM RaceTrack Memory
  • 18.8.3 IBM and TDK MRAM R&D Project
• 18.9 MagIC Technologies (and IBM)
• 18.10 MagLabs
• 18.11 MagSil
• 18.12 Micromem
• 18.13 NEC
  • 18.13.1 NEC Domain Wall Spin Polarized MRAM
  • 18.13.2 Magnetic Primitive Cell for SoC Libraries Using MRAM/CMOS Process (NEC)
  • 18.13.3 Dual Port 5T2MTJ Cell in SoC MRAM Technology (NEC)
  • 18.13.4 NEC Toggle Mode MRAM
  • 18.13.5 2T1MJT Cell for Write Current Control (NEC)
  • 18.13.6 5T2MTJ Cell for GHz Access Time (NEC)
• 18.14 Non-Volatile Electronics (NVE)
• 18.15 Renesas
• 18.16 Samsung
• 18.17 TDK and IBM MRAM R&D Project
• 18.18 Toshiba
  • 18.18.1 Perpendicular TMR STT MRAMs (Toshiba)
  • 18.18.2 Degradation Mechanisms in MgO STT MRAM (Toshiba)
  • 18.18.3 Reducing Variation in STT MRAM Switching Current (Toshiba)
• 18.19 TSMC

Bibliography

Overview | Contents

To order "Magnetic RAM (MRAM) Product, Development & Technology, March 2009
 (STT-MRAM, Toggle/Field Write MRAM, Hybrid MTJ-CMOS Logic, Test Applications,
Roadmaps, Reliability, Modeling, Multi-Bit, Architecture)":

Contact Memory Strategies or
Complete the form below and send (by e-mail, fax, or post) the form and your check, bank transfer, or purchase order for $975. ($850 if a Technical Market Analysis has been ordered from Memory Strategies in the past year.).

ORDER FORM: Please send ______ copies of  "Magnetic RAM Product, Development & Technology, March 2009" to:

Report Format

____ PDF. Will be sent by email. Please send your order by email, if possible. Printing hardcopy from PDF is permitted.

____ (Hardcopy of report only available for shipping within USA. We apologize for any inconvenience.
           Report will be sent by 2-Day FedEx. Please send all information requested above.)
         If you wish both PDF and Hardcopy, please add an additional USD200 to your order

Submit Order and Payment Information via:
    Email: info@memorystrategies.com, or
    Fax:    +1 512 260 6220
    Post:
        Memory Strategies International,
        16900 Stockton Drive,
        Leander, Texas 78641, U.S.A.

To pay by:

• Credit Card: please fax credit card information to +1 512 260 6220
• Bank Transfer: please send in your order and request transfer details.
• Purchase Order: submit purchase order details with order.

For more information, please Contact Memory Strategies

| Home | Reports | Seminars | Consulting | Contact Us | About Us | Site Map |

Memory Strategies International, 16900 Stockton Drive, Leander, TX, USA, 78641;   512.260.8226 (phone), 512.260.6220 (fax). Send questions or comments about this website to webmaster@memorystrategies.com. Copyright © 2009 Memory Strategies International. All rights reserved. Legal stuff. Last Modified: August, 2009.