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Nanocrystal Flash Memories
(NAND, NOR, Embedded Flash, Nanodot, Hi-K, Self-Assembly, FinFlash, Metal Nanocrystal, Tunnel Engineering)
May 2009

Development efforts continue in nanocrystal non-volatile memories particularly in the embedded memory area. Both NOR and NAND flash are in development using nanocrystals. Several major companies are in development and there are many projects ongoing in major research labs around the world. Particular effort has been focused recently on: development of memory macro's containing nanocrystal memory cells, developing high-k blocking materials for the IPD in these memories, use of metal nanocrystals in memory cells, cells with multiple layers of nanocrystals, tunnel engineering and development of vertical nanocrystal structures such as FinFlash memories. Significant efforts continue on modeling the nanocrystal memories and on reliability studies including those reporting the results of irradiation of the memory.  60+ pages

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Table of Contents

Executive Summary

Table of Contents

1. Overview of Current Trends in Nanocrystal Memory

2 Some Markets and Applications For Silicon Nanocrystal Memory

• 2.1 Nanocrystal Memory Developers in Various Markets
  • 2.1.1 NC Developers in the NAND Flash Memory Market
  • 2.1.2 Nanocrystal Memory Developers in the NOR Flash Memory Market
  • 2.1.3 Nanocrystal Memory Developers in the Microcontroller Market
• 2.2 Applications Targeted for Nanocrystal Memories
  • 2.2.1 Standalone Nanocrystal Flash Memory in Scaled Technologies
  • 2.2.2 Nanocrystal Memory for Standalone NAND Flash
  • 2.2.3 Nanocrystal Memory for Embedded NOR Flash
  • 2.2.4 Radiation Studies of Nanocrystal NV Memory

3.0 NanoCrystal Cells in Development in NOR Flash Memory Arrays

• 3.1 Cylindrical Bit Cell for 90 nm 4-Mb Si-NC NOR Flash Memory (Numonyx)
• 3.2 Split Gate Cell in 128-KB NOR Flash Memory Array (Freescale)
• 3.3 16-Mb NOR Flash Fabrication and Integration (ST Microelectronics)

4 Oxide Studies for Nanocrystal Memory

• 4.1 High-K Blocking Oxide for Nanocrystal Memory
  • 4.1.1 Overview of use of High-K Blocking Oxide for Nanocrystal Memory
  • 4.1.2 High-k Al2O3 as Blocking Oxide for 3-D Self-Assembled NC Memory (U. of Texas)
  • 4.1.3 Study of Integrated Arrays of Silicon NC Memories Using HfAlOx IPD (CEA-LETI)
  • 4.1.4 Using Various High-K IPD on a Silicon NC Memory (CEA-LETI)
  • 4.1.5 Multi-Gate FET with Al2O3 Blocking Dielectric and TiN NC (Nat. Chiao Tung U.)
  • 4.1.6 Fabrication of Hafnium Silicate Sol-Gel Nanocrystal Memory (Nat. Chiao Tung U.)
• 4.2 Tunnel Oxide Engineering on Nanocrystal Flash Memories
  • 4.2.1 Overview of tunnel oxide engineering of NC Memories
  • 4.2.2 Variable Oxide Engineering for NC Memories (U. of Texas)

5.0 Nanocrystal Self Assembly

• 5.1 Nanoscale Ordering of Ge Nanocrystals (Queensland Univ. of Tech., Brisbane)
• 5.2 Self-Assembly of Nickel NC Memories Using Block CoPolymer (U. of Texas)
• 5.3 Chaperonin Protein Lattice for NC Self Assembly (U. of Texas, U. of Oklahoma)
• 5.4 Si-NC Self Assembly using Dissociation of SiH2C12 Gas (Feng Chia U.)
• 5.5 Forming Regular Spherical Patterns Using Block Copolymers in a Wafer Fab (MIT)
• 5.6 Pattern Formation in DiBlock Copolymer Materials for NC Self-Assembly (IBM)

6.0 Alternative Nanocrystal Materials

• 6.1 Memory Devices with Germanium Nanocrystals
  • 6.1.1 Using Ge-Si Shell Nanocrystal Structures for Improved Data Retention (U. of Texas)
  • 6.1.2 Ge NC in a Tri-Layer Gate Stack Memory (Nat. Univ. of Singapore)
  • 6.1.3 Effect of Charging on Current Conduction in Ge NC Memory (Nanyang Tech. U.)
  • 6.1.4 Improved Retention Using Ge/Si Hetero-NC ( U. of Calif., Riverside)
  • 6.1.5 Ge NC Memory made by Ion Implant and Anneal (Dongguk Univ.)
• 6.2 Platinum Nanocrystals in Double Layer Configuration (Applied Materials, IIT)
• 6.3 Memory Using RuO2 Nanocrystals with Wide Memory Window (Chang Gung Univ.)
• 6.4 TiN Nanocrystals Laminated with Al2O3 (Chang Gung Univ.)
• 6.5 Reliability and Performance of Devices with Tungten Nanocrystals (IIT)
• 6.6 Characterization of Devices with Au NC (IIT)

7.0 Physical Properties and Fabrication of NC Memories

• 7.1 Methods of Fabrication of NC Memories: LP-CVD vs. Ion Implant (Peking U.)
• 7.2 Electron Transport and Photonic Properties of Silicon NC (Tokyo Inst. of Tech.)

8.0 Reliability of Nanocrystal Memories

• 8.1 Charge Loss Under Heavy Ion Radiation of NC Cell (Univ. of Padova)
• 8.2 Reliability of Crystalline & Amorphous Nanoparticles in MOS (U. Auto. de Baja)
• 8.3 Reliability Study of Nanocrystal Memories with High-k Dielectrics (Texas A&M Univ.)
• 8.4 Analysis of NC Memory Cells in Linear and Subthreshold Regions ( U. of Padova)
• 8.5 Data Retention Study for Split Gate Nanocrystal Flash Memory (Freescale)
• 8.6 Irradiation Studies of Nanocrystal Capacitors and Transistors (Nat. Tech. U. Athens)
• 8.7 Threshold Voltage Instability in NV NC Memories During Retention (U. of Padova)
• 8.8 Performance and Reliability of NC NMOS Transistors in CMOS (Tsinghua U.)

9.0 Test and Characterization of Nanocrystal Memory

• 9.1 Programming Characteristics of Triple Layer Silicon NC Memory (Tsinghua U.)
• 9.2 Threshold Voltage Variation in NC NV Memories (STMicro. & U. of Padova)

10.0 Using Nanocrystals to Improve SONOS Memory Characteristics

• 10.1 Embedding Self-Assembled Si-NC in Storage Nitride (Feng Chia)
• 10.2 SONOS Memory with Silicon NC Layer between Double Tunnel Oxides (Toshiba)
• 10.3 Impurity Trap Memories (ITM) for Data Retention Improvement
  • 10.3.1 Nano-Trap Memories Using Ti Additives (NEC)
  • 10.3.2 Nanotrap Memories Using Negative Conduction Band Offset Materials (Samsung)

11. Multiple Layer NC Gates

• 11.1 Double Layer Stacked Heterometal NC of Ni/Au (KAIST)
• 11.2 Double Gate and Tri-Gate FinFET Si-NC 10 nm Memories (CEA-LETI)
• 11.3 Tri-Gate FinFlash SN Memory (CEA/LETI)

12 Vertical Structures for Nanocrystal Memories

• 12.1 Gate-All-Around Vertical NC Flash Cell (U. of Texas, Austin)
• 12.2 Improving the P/E Window using a NC FinFET (Sungkyunkwan U.)
• 12.3 Vertical Flash Memory with SiGE Nanocrystals Grown on a Pillar (U. of Texas)
• 12.4 Vertical FinFET Structure for Nanocrystal Memory

13.0 Modeling of the Nanocrystal Device and Process

• 13.1 Model to Calculate Tunnel Current in NC Cells(Air Force Res. Lab.& U.of Missouri)
• 13.2 Model for Electrical Behavior of NC Trigate Fin-FET Structures (CEA-LETI-Minatec)
• 13.3 Model for NC FinFlash Memories Under Uniform Stress (CEA/LETI)
• 13.4 Charge Retention Model for Metal NC Retention Characteristics (Chin. Acad. of Sci.)
• 13.5 3-D Simulator for Metal Nanocrystal Flash Memory Design (IIT)
• 13.6 Models for Transient Simulation of NC Flash Cells using Cadence (Nanyang Tech. U.)
• 13.7 TCAD Simulation of NOR NC Memories (CEA-LETI)
• 13.8 Simulation for Design Optimization in a Metal NC Memory (Cornell U. )
• 13.9 Simulation Model for Nanocrystal Flash Memory (Tsinghua U.)
• 13.10 Analytical Model for Trapping Site Storage (CEA-LETI)

14.0 Basic Research into Nanocrystal Memories

• 14.1 Gate-All-Around Si Nanowire SONOS Using Si NC/Ni for storage (A-Star, Singapore)
• 14.2 Model for Single Electron Tunneling in Nanocrystal Memories (Catania)
• 14.3 Electrostatics of Metal Nanocrystal - Carbon Nanotube Memories (Cornell U.)

15.0 Developers and Vendors of Nanocrystal Memories

• 15.1 Atmel and CEA-LETI
• 15.2 Freescale
• 15.3 IBM
• 15.4 Micron Technology
• 15.5 NEC
• 15.6 Numonyx
• 15.7 ST Microelectronics
• 15.8 Samsung
• 15.9 Toshiba

Bibliography

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