Report: NAND and NOR Nanocrystal Flash Memory, July 2006

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NAND and NOR Nanocrystal Flash Memory -
July 2006

Development effort in Nanocrystal memory cells is ongoing with at least 5 of the top 10 flash memory suppliers as well as in several embedded memory suppliers and a significant number of universities and labs.. Nanocrystal storage is being forecast by some as a technology for the 45 nm technology node or beyond as an extension of the floating gate or trapping site storage flash memories. Current effort can be found in metal nanocrystals, high-k dielectric constant oxide replacement materials, and in novel vertical gate devices using nanocrystals. 40+ pages.

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NAND and NOR Nanocrystal Flash Memory -
July 2006

Table of Contents

1. Overview of Current Trends in Nanocrystal Memory

2. Some Markets For Silicon Nanocrystal Memory
2.1 Flash Memory Market
2.2 NAND Flash Markets for Nanocrystal Memories.
2.3 NOR Flash Markets

3 Overview and Technology Background of Silicon Nanocrystals

4 Process Technology and Assembly for Nanocrystal Memories
4.1 Chaperonin Protein Mediated Assembly of Nanocrystals
4.2 Aerosol Fabrication of Silicon Nanocrystals
4.3 Fabrication of Double Row Nanocrystal Memory

5.0 Reliability Issues for Nanocrystal Memories
5.1 Silicon Nanocrystal Retention Time in Terms of NC Density: Fluctuations to SILC
5.2 Investigation of Data Retention with Pulsed Voltage Programming

6.0 Materials Modifications: Metal Nanodots and Hi-k Dielectrics
6.1 Hafnium Oxide (HfO2) Nanocrystal Memory
6.2 Silicon Nanocrystals Embedded in SiN
6.3 Silicon Rich Oxide (SRO) Trapping Mechanism
6.4 WN Nanocrystals with Stacked Tunnel Barrier
6.5 Nickel NC with HfO2 Dielectric
6.6 HfO2 NC Memories
6.7 HfAlO Oxides with Ge NC

7.0 Novel Structures for Nanocrystal Memories
7.1 Vertical FinFET Structure for Nanocrystal Memory
7.2 Discrete Trap Memory using Double Tunneling Junction with Silicon Nanocrystals
7.3 Double Gate Nanocrystal Memories
7.4 Separated Gate Source Side Injection Nanocrystal Memory

8.0 Modeling of the Nanocrystal Process
8.1 Modeling Program/Erase Dynamics of a Nanocrystal Memory with Uniform Tunneling
8.2 Modeling Dual Bit Discrete Trap Flash Memories
8.3 Modeling the Statistical Properties of Threshold Voltage Shift for NC Memory Cells

9.0 Developers and Vendors of Nanocrystal Memories
9.1 Atmel and LETI
9.2 Freescale
9.3 STM and Philips
9.4 Renesas
9.5 Spansion
9.6 Samsung

10.0 Universities and Labs Working with Nanocrystal Memory
10.1 NanYang Technical U. (Singapore)
10.2 Politechnico di Milano
10.3 CEA-LETI Labs
10.4 University of Rome
10.5 U. of Texas
10.6 Cornell University
10.7 University of Tokyo
10.8 National University of Singapore
10.9 National Chiao-Tung University

Bibliography:

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