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Trapping Site Storage Flash Memory - Applications, Technology, Reliability,
Vendors
Nitride, NAND, NOR, SONOS, NROM, MONOS, eSONOS, eMONOS, TANOS
February 2008
The market for Flash memory has been poor in the past few months due to oversupply and also due to some targeted applications reducing their purchasing. The decline in the market is not necessarily bad news for development of new flash memory technologies such as the next generation trapping site storage.
Applications for the NAND flash are high density data storage such as solid state drives, MP3 players, and removable flash cards for digital cameras and camcorders. Applications for the NOR flash include the traditional code storage in mobile phones, set top boxes and digital television and also higher density applications such as navigation systems in automotive electronics and multimedia cell phones. Applications for processors with embedded flash memory include smart cards, RFID and USB keys. Processors for the automotive market also use embedded flash as well as processors for motor control.
Two bit and four bit trapping site storage devices have been developed to increase density options for Flash memory. Both embedded and standalone flash is in production in 90 nm technology. Band-gap engineering is reducing leakage while improving programming properties. Operational properties are being studied and modeled and effects such as the second bit effect are being understood.
New cell structures are being developed to improve speed and data retention. Some innovative nanowire SONOS devices have been described. FinFET architectures, some with double gates, are being used to improve the characteristics for trapping site storage. Thin Film Transistor technology is permitting multiple layer stacking of SONOS flash devices.
High-k dielectrics such as AlO, HfO2 and HfAlO along with high workfunction gates are improving the characteristics of the trapping site memories. These have permitted devices down to 30 nm technology to be explored leading to potential for 64 Gb flash technology.
A number of foundries are now providing trapping site storage either for dedicated customers or for the general market. Several companies are in production with the technology. 100+ pages.
Trapping Site Storage Flash Memory - Applications, Technology, Reliability,
Vendors
Nitride, NAND, NOR, SONOS, NROM, MONOS, eSONOS, eMONOS, TANOS
February 2008
Table of Contents
Table of Contents
1.0 Executive Overview:
2.0 Overview of Flash Memory Market and Applications for SONOS/MONOS
2.1 Overview of Flash Memory Market Potential for SONOS/MONOS
2.2 The NAND Flash Market and Applications for SONOS/MONOS
2.2.1 Overview of NAND Flash Market Potential for SONOS/MONOS
2.2.2 Overview of NAND Flash Applications for SONOS/MONOS:
2.2.3 Virtual Hard Disk Drives
2.2.4. Solid State Drives (SSD)
2.2.5 Digital Still Cameras:
2.2.6 CamCorders
2.2.7 MP3 Players
2.2.8 Multi-Media (Video, Games, GPS Maps)
2.3 The NOR Flash Market and Applications for SONOS/MONOS
2.3.1 NOR Flash Market Potential for SONOS/MONOS
2.3.2 Overview of NOR Flash Applications for SONOS/MONOS
2.3.3 Automotive Communications Systems
2.3.4 Automotive Navigation Systems
2.3.5 Multimedia and Feature Cell Phones
2.3.6 Mobile Phone Memory Security Features
2.3.7 Removable Flash SIM Memory Cards
2.4 Market and Applications for Embedded MONOS and SONOS
2.4.1 Markets and Applications for Embedded Nitride Storage Flash
2.4.2 Smart Card, RFID and USB
2.4.3 Automotive Microcontrollers
2.4.4 MONOS Memory Cell Integrated with TFT Liquid Crystal Display for
Mobile
2.4.5 Motor Control
3.0 Trapping Site Flash Cell Size by Technology Node
3.1 Various Nitride Storage Cell Sizes for Different Technologies and Flash
Types
4.0 Embedded Nitride Storage Flash Product and Technology (MONOS/SONOS)
4.1 Embedded SONOS Devices
4.1.1 eSONOS Technology (Cypress)
4.1.2 4-Mb eSONOS Flash in 180 nm CMOS logic (Tsinghua U.)
4.1.3 eSONOS for Embedded Functions (Chartered Semiconductor)
4.2 Embedded MONOS Devices (Renesas)
4.3 Embedded NROM Devices (Saifun, NEC)
4.4 Embedded Silicon-on-ONO Flash Memory (Samsung)
5.0 Background of Trapping Site Storage Technology
5.1 NOR Flash Trapping Site Technology
5.1.1 Single Sided SONOS "PHINES" Flash (Macronix)
5.1.2 Double-Bit Phines" SONOS (Macronix)
5.1.3 NROM NOR Using Back Bias HHI and Forward Bias Assisted CHEI
(Promos)
5.1.4 Two-bit/Cell NOR MirrorBit SONOS (Spansion)
5.1.5 P-Channel 60 nm SONOS NOR Flash Cell (Genusion)
6.0 Trapping Site Storage NAND Flash Product and Technology
6.1 Bandgap Engineered Nitride SONOS(BE-SONOS) for NAND Flash(Macronix)
6.2 BE-SONOS With ONO above Charge Layer and Injection From Top Gate(Macronix)
6.3 A New Impact Ionization Program and BB Tunnel HH Erase for NAND (Macronix)
6.4 TANOS NAND Flash
6.4.1 Charge Loss Through Lateral Spreading in TANOS (Samsung)
6.4.2 40 nm TANOS NAND Flash SONOS Using Asymmetric Source/Drain(Samsung)
7.0 Trapping Site Storage With Four Bits Per Cell
7.1 Overview of Trapping Site Storage with Four Bits Per Cell
7.2 Nitride Storage SONOS with Four Physical Bits per Cell (Samsung)
7.3 NROM Type Flash with Four-bit per Cell (Two Physical Bits and Two MLC)
7.3.1 8-Gb NROM with 4-bit/cell (2 Physical Bits & 2 MLC) (Saifun,
Netanya, SMIC)
7.3.2 Mirror Bit NOR Quad Flash with Two Physical/ Two Multilevel
(Spansion)
7.3.3 NROM Type Nitride Storage - 2 Physical/ 2 Multilevel (Saifun and
Macronix)
7.4 Trapping Site Storage with Four Bit/Cell Using High-k Trapping Layer
7.4.1 4-Bit/Cell(2-P/2-ML)with Partially Crystallized HfO2 Trapping
Layer(SKKU,NUS)
7.5 Four Physical Bit Per Cell Trapping Site Storage
7.5.1 NROM Type Nitride Storage Data Flash (Saifun)
8.0 New Cell Structure Technology Development for Trapping Site Storage
8.1 Dual Charge Storage Layers for Multi-Level Cell Storage (SKKU & NUS)
8.2 Gate-All Around Twin Nanowire
8.2.1 Gate-All Around Nanowire Twin SONOS Device(Inst.uElec., Nat. U.-
Singapore)
8.2.2 Gate-All Around Twin Nanowire SONOS (Samsung)
8.3 Quantum Confinement Effect for Hole Injection Efficiency in MONOS (Hitachi)
8.4 Multi-Bit/Cell Operation of SONOS with Wrapped Select Gate (Nanya&N.ChiaoTung)
8.5 Nitride Trapping Non-Volatile Gated Diode Cell (Macronix)
8.6 Unified Floating Body DRAM & NVM Using PD-SOI SONOS FinFET (KAIST)
8.7 SONOS with Spacer Storage Nodes on Sidewalls of Recessed Channel (KyungpookU.)
8.8 An Array-Nitride Sealing Process to Eliminate Vt Loss (Macronix)
9.0 High-k Dielectric and High Workfunction Gate For Trapping Site Storage
9.1 SONOS Using High-k Dielectric Hafnium Silicate as the Trapping Layer.
9.1.1 Hafnium Silicate in a TFT Flash Memory (N. Chiao Tung U.)
9.1.2 SONOS with HfO2 Storage Layer & Dual SiO2/Si3N4 Tunnel Layer (SKKU&NUS)
9.1.3 Double Tunnel MONOS using High-k HfO2 Dielectric Storage Layer (NUS)
9.1.4 Hf-Based Oxides as Storage Layer in SONOS/NROM (CEA-LETI)
9.1.5 HfAlO for Storage, Dielectric and Blocking Layers of a SONOS Device
(NUS)
9.2 MATHS (TANOS)(MANOS) Nitride Storage
9.2.1 Mechanism and Erase Characteristics of MANOS Memories (Macronix)
9.2.2 MATHS, MHTHS and SONOS Comparison (Spansion)
9.2.3 Integration of 30 nm Multi-Level NAND Flash using 38 nm TANOS
(Samsung)
9.2.4 32-Gb multi-level NAND Flash Using 40 nm TANOS (Samsung)
9.2.5 Multi-Level 63 nm NAND Flash Memory Using TANOS Technology
(Samsung)
9.3 ZnO and AlxGa(1-x)N in Charge Trap Devices (Samsung)
10.0 3D and FINFET Trapping Site Storage
10.1 BE-SONOS FinFET NAND Flash Using Fin Tip Field Enhancement (Macronix)
10.2 Double-Gate & Tri-Gate FinFET SONOS Flash(STMicroelectronics, CEA-LETI,
IMEC)
10.3 SONOS NAND Using Body-Tied FinFET BE-SONOS Flash (Macronix)
10.4 Tri-Gate SONOS NAND FinFET P+ Gate Array (Qimonda)
10.5 Bulk P-Channel FinFET SONOS for NOR and NAND (Samsung & Seoul Nat. U.)
10.6 Paired FinFET Charge Trap Memory (Samsung)
10.7 Integrated P+ Gate FinFET SONOS with High-k Blocking Dielectric (Samsung)
10.8 SONOS NOR Arrays Using Body-Tied FinFET Cell (Samsung)
11.0 TFT Nitride Trapping Site Storage
11.1 TFT MONOS on Glass Substrate (ITRI and STAR)
11.2 Three Dimensional TFT SONOS
11.2.1 Bandgap Engineered TFT NAND SONOS Flash (Macronix)
12 3-D Stacking Using Through Hole Vias
12.1 3-D Stacking of NAND Flash Using Single Crystal Silicon Layers
(Samsung)
12.2 3-D Through Hole Vias for SONOS NAND Flash (Toshiba)
13. Reliability Issues for Trapping Site Storage Memory
13.1 Disturb Due to Impact Ionization While Programming a Neighboring Cell
(Macronix)
13.2 Hydrogen Diffusion/Invasion in Nitride Trapping Flash Memory (Macronix)
13.3 Profiling Charge Distributions in NROMs using Id-Vgs Based Tools (Saifun)
13.4 Mechanism of Drain Disturb (Indian Inst. of Tech. and Purdue U.)
13.5 Reliability Comparison of FinFET and Planar SONOS NAND Devices (Samsung)
13.6 Reliability Study of Bandgap Engineered SONOS (Macronix)
13.7 Vertical Position and Type of Charge in SONOS During P/E (DIEGM)
13.8 Reliability of SONOS with Different Tunnel Oxides (HTO type)(Nat. Def.U.
Taiwan)
13.9 P/E & Retention Characteristics of P+ & N+ Poly Gate SONOS (Powerchip)
13.10 Polarity Dependent Device Degradation in SONOS Transistors (Seoul Nat. U.)
13.11 Trapped Charge Distribution and Type in 180 nm SONOS (Tsing Hua U.)
13.12 Reliability of High K and WF Eng. MONOS (N. Chaio-Tung&Nat. Tsing Hua U.)
13.13 Split Gate SONOS Flash Cell Reliability (Indian Inst. of Tech.)
13.14 Overerase Issues in Scaled Nitride Storage Flash Memory (Macronix)
13.15 Lateral Charge Profile in SONOS EEPROM (Renesas & Indian Inst. of Tech)
13.16 Leakage Mechanisms in the ONO Layer of a SONOS Cell (Nat. Chiao Tung U.)
13.17 FinFET Data Retention Study (Samsung)
13.18 Stress Induced Charge Loss in SONOS (Macronix & Nat. Chiao-Tung U.)
13.19 NROM Data Retention Studies (Macronix)
13.20 Endurance and Data Retention of CHE and HHI SONOS (Ind. Inst. of Tech)
13.21 Electron and Hole Trap Sites in Embedded MONOS Memories (Hitachi)
13.22 Lateral Charge Distribution in 2-bit Twin SONOS (Seoul Nat. U.)
13.23 Error Detection in NROM Flash Devices (Macronix and Saifun)
13.24 Read Disturb in Two-Bit/Cell SONOS (Macronix)
13.25 Second Bit Effect in Two-Bit/Cell SONOS (Indian Inst. of Tech)
14.0 Modeling and Simulation for Trapping Site Memories
14.1 Model of Eff. Vertical Trap Location for Different Materials (SKKU, NUS,
Fudan U.)
14.2 Profiling the Nitride Trap Energy Distribution in a SONOS Flash (Macronix)
14.3 Trapping Dynamics Using Gate/Channel Sensing Transient Analysis (Macronix)
14.4 Measuring Carrier Mobilities in Insulators Like Silicon Nitride (Renesas)
14.5 Nitride Charge Evolution in NROM Flash Devices (U. de Ferrara & U di Modena)
14.6 Transient Analysis Method for Trapping Dynamics in SONOS (Macronix)
14.7 Numerical Simulation of Charge Retention in SONOS (Macronix & Nat.
Chiao-Tung)
14.8 A TCAD Simulator for SONOS Flash Memories (Ind. Inst. of Tech.)
14.9 Transient Current Models for SONOS Time and Field Dependence (Nat.
Chiao-Tung)
14.10 Physical Model to Predict Retention in Nitride Storage Memory (IMEC & KU
Leuven)
14.11 Modeling Effects in SONOS Due to Random Telegraph Noise(RTN)(Macronix)
14.12 Modeling Effects of Small Charged Regions in SONOS Memories (CEA-LETI)
14.13 Physical Mechanisms of Vt Shift After Cycling in NROMs (Tower)
15. Vendors and Developers for Trapping Site Storage Flash
15.1 Cypress
15.2 Macronix
15.3 Qimonda NROM
15.4 NEC Embedded NROM
15.5 Powerchip SONOS Flash
15.6 Promos SONOS Cell Research
15.7 Renesas Embedded MONOS
15.8 Samsung TANOS NAND Flash
15.9 Spansion MirrorBit NROM Type Flash
15.9.1 Spansion RoadMap for MirrorBit NROM Type Flash
15.9.2 Spansion MirrorBit Quad Flash in 65 nm
15.9.3 1Gb 2-bit/cell NOR MirrorBit SONOS (Spansion)
15.9.4 Spansion Foundry Capacity
15.9.5 Spansion Acquires Saifun and Partners with SMIC
15.10 Toshiba SONOS NAND Flash
15.10.1 Toshiba Production of Flash Memory
15.10.2 Toshiba Vertical SONOS Technology
16 Foundries with Trapping Site Storage Flash
16.1 Chartered Semiconductor (Shanghai)
16.2 Grace Semiconductor (Shanghai)
16.3 Hua Hong NEC (China)
16.4 SMIC (China)
16.5 Tower (Israel)
16.6 TSMC (Taiwan)
16.7 UMC (Taiwan)
17.0 Vendors of Nitride Storage Flash IP
17.1 Simtek
17.2 eMemory NeoFlash SONOS
17.3 Saifun
Bibliography:Bibliography
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