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A Memory Strategies Focus Report

Trends in Phase Change Memory
(Applications, Development, Modeling, Circuits, Reliability, Test)
April 2010

The Phase Change Memory (PCM, PC-RAM) is an interesting new non-volatile RAM technology being primarily considered as both a supplement or replacement in flash memory applications and as a non-volatile RAM for integrating with logic technology to replace multiple other conventional memory types.

Phase Change Memory is essentially a "Unified Memory", that is, a part that functions both as a non-volatile memory and also as a random access memory. The physical basis for this technology is the phase change of a material between two resistance states. Several companies are in development on potential products based on this technology. Many other companies, research labs and universities have published technical studies of the properties of this new memory technology. Many of these recent studies on development, test, reliability, modeling, applications and characteristics of the PCM are discussed in this report. Applications considered for PCM include: portable and wireless handheld systems, main memory systems and computing platforms, disk cache in servers and flash file systems, combined with flash in SSD, military and space applications, and some automotive and consumer applications. Potentially cost effective integrated process technologies for the PCM have been shown from 90 nm down to 45 nm and below. High density 3D stacked cross-point arrays can potentially be made with the PCM.

Various issues being examined for this new memory include: resistance drift due to structural relaxation in the amorphous state, data loss due to spontaneous crystallization in the amorphous state, techniques to reduce write current for the RESET operation, low frequency noise fluctuations in the amorphous state, and characterizations of the crystallized SET state. Access devices discussed include a bipolar junction transistor (BJT) and a MOS FET along with diodes for use with stacked cross-point arrays. Investigation continues of materials with various concentrations of GeSbTe to optimize the PCM characteristics. The potential for multi-level cell PCM technologies have been studied. A significant amount of effort has been spent on developing models for the phase change material, for the PCM cells and for the design of PCM devices. Significant effort continues on test, reliability and characterization of the PCM. As prototypes have been developed, efforts on design have included various circuits useful with the PCM cell such as pulse shapers and write drivers. Studies of system related reliability techniques have been conducted. The various developers and suppliers of PCM are noted.

115+ pages.

We also have focus reports available on Ferroelectric memory & Magnetic memory

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Table of Contents - Trends in Phase Change Memory, April 2010

1.0 Overview of Phase Change Memory and Its Characteristics

2.0 Applications For Phase Change Memory

• 2.1 Main Memory System Using PC-RAM (Penn State University)
• 2.2 Computing Platforms
• 2.3 Using Phase-Change Memory in Caches
• 2.3.1 Using PCM in a as Disk Cache in Servers (University of Michigan)
• 2.3.2 Hybrid Non-Volatile Memory Caches including MRAM, PC-RAM and SRAM(IBM)
• 2.4 Flash File System Based on Hybrid Architecture of PCM and NAND(KAIST)
• 2.5 Including PCM in Stacked TSV DRAM and MPU Systems (Univ. of Florida)
• 2.6 PC-RAM as NOR Flash Memory Replacement
• 2.7 Air, Military and Space Applications (BAE Systems)
• 2.8 Automotive and Consumer Applications (CEA/LETI-MINATEC)
• 2.9 PC-RAM and DRAM Hybrid in Main Memory Architecture in Computing Systems
• 2.10 Low Power Portable Handheld Systems
• 2.11 Industrial and Embedded Applications
• 2.12 Solid State Storage Subsystems
• 2.13 Set-Top Boxes
• 2.14 Smart Metering

3.0 Technology Overview for the Phase Change Memory

• 3.1 Basic Operation of PCM
• 3.2 Cell Sizes vs. Technology for Phase Change Memory
• 3.3 Overview of PCM Technology Roadmap
• 3.4 PCM Scaling Trends
• 3.5 Scaling Behavior of GST Technology
  • 3.5.1 PCM Scaling Behavior Using a Pseudo 3-Terminal Device (Samsung,Stanford)
  • 3.5.2 System Level Modeling for Scaling of PC-RAM (Penn State Univ.)

4.0 Integrated Process Technologies For Phase Change Memory

• 4.1 1-Gb PCM in 45 nm CMOS Technology (Numonyx)
• 4.2 Integrated PCM Process Module Embedded in 90 nm 6ML CMOS (STM, Numonyx)
• 4.3 GST PCM with Diode Switch (Samsung)
  • 4.3.1 60 nm 512-Mb PCM Technology (Samsung)
  • 4.3.2 Two Bit, Four Level 90 nm PCM (Samsung)
  • 4.3.3 512-Mb Diode Switch PC-RAM (Samsung)

5.0 Issues for Phase Change Memory

• 5.1 Resistance Drift Due to Structural Relaxation
  • 5.1.1 Time Aware Memory Sensing for Resistance Drift Issues (Rensselaer Institute)
  • 5.1.2Structural Relaxation in the Amorphous State of a MLC PCM Array (Polit. di Milano)
  • 5.1.3Study of Resistance Drift and Its Dependence on Temperature (Politecnico di Milano)
  • 5.1.4Characterization of Structural Relaxation in Amorphous PCMs (Politech. di Milano)
  • 5.1.5A Study of Structural Relaxation in PCM Cells (Politecnico de Milano)
  • 5.1.6Structural Relaxation Model to Explain PCM Drift (Intel)
  • 5.1.7Temperature Acceleration of Relaxation of Amorphous PCM Cell(Polit. di Milano)
• 5.2 Data Loss from the Amorphous (RESET) State of the Phase Change Memory
  • 5.2.1 Multiple Amorphous States for Undoped Ge15Sb85 Bridge PCM (Aachen Univ.)
  • 5.2.2 Mechanisms of Data Retention Loss Due to Spontaneous Crystallization(IBM, Macronix)
  • 5.2.3 TEM Observations of Slow Quenching Crystallization Behavior (Samsung, U. of Texas)
  • 5.2.4 Parasitic Crystal Path in SET Related to Anomalous Tail Bits in RESET(U.diFerrara)
• 5.3 Reducing Write Current in Phase Change Memory
  • 5.3.1 Reducing Thermal Conductivity in PCM to Reduce Programming Current (Samsung)
  • 5.3.2 Lower RESET Current Using TiO2 Insert in Confined GST PC-RAM (U. Khon Kaen)
  • 5.3.3 Confined PCM for Low Write Current Sub-20nm Technology Generation (Samsung)
  • 5.3.4 Reducing Write Current Using a Cross-Spacer (ITRI, PCS, ProMOS, Nanya, Winbond)
  • 5.3.5 Simulation of Interface Thermal Resistance Increases in PCM (Stanford U.&Intel)
• 5.4 Oscillatory Behavior (Noise Fluctuations) in an Amorphous State PCM
  • 5.4.1 Current Fluctuation Effects of Scaled PCM (Politecnico di Milano)
  • 5.4.2 Low Frequency Noise in Amorphous State of PCM (Numonyx)
  • 5.4.3 Relaxation Oscillation Study of GST PCM Devices (University of Toledo)
  • 5.4.4 Model of Low Frequency Current Noise in PCM Devices (Numonyx)
  • 5.4.5 Oscillatory Behavior of a PCM in the Amorphous State (Politechnico di Milano)
  • 5.4.6 Reducing Resistance Fluctuations using a CMP Process (Chinese Acad. of Sci.)
• 5.5 Dynamic Resistance of the PCM Cell
  • 5.5.1 Measurements of Dynamic Resistance of the PCM Cell (IBM, Macronix)
  • 5.5.2 Dynamic Resistance - A New Characterization Metric for PCM (IBM, Macronix)
  • 5.5.3 Analytical Model for RESET Operation of PCM (IBM, Macronix)

6.0 Characterization of the SET Operation in PC Memories

• 6.1 Analysis of PCM Transient Current Waveform During Crystallization (A*STAR)
• 6.2 Characterization of PCM Shunt Percolation Path (U.di Ferrara)
• 6.3 Characterization of 256-Kb GST PCM arrays in 180 nm CMOS (Qimonda)
• 6.4 Characterization of the SET Operation in a PCM (Univ. di Roma)

7.0 Phase Change Memory Using BJT Access Devices

• 7.1 Overview of MOS and BJT Selectors for PCM (Numonyx)
• 7.2 Two Bipolar TRansistor and Two PC Device Cell Structure PCM (Fudan U.)
• 7.3 Vertical BJT Access Device in 180 nm Technology (IBM, Macronix)
• 7.4 90 nm 128-Mb PCM with BJT and Multilevel Storage (Numonyx, STM, U. of Pavia)

8.0 Phase Change Memory Cross-Point Cells with Scaled Diode Switches

• 8.1 Stacking PCM in Cross-Point Array with Ovonic Threshold Switch (Intel, Numonyx)
• 8.2 Cross-Point PCM Using Polysilicon Selection Diode (Hitachi)
• 8.3 Cross-Point Array Using p-GST to n-Si Heterojunction Diodes (Fudan Univ.)
• 8.4 Circuit and Design of Scaled Diode Switch PCM (Rensselaer Polytechnical Institute)
• 8.5 Comparison of Current Drive of PN Diodes vs. MOSFETs with PCM (Hong Kong U.)
• 8.6 Phase Change Memory Cross-Point Cell with Doped Ge Nanowire Diodes (Stanford)
• 8.7 Physical model for PCM with Diode Access Device (HKUST)

9.0 Novel Materials for Phase Change Memory Cells

• 9.1 Thermal Conductivity of Ge1Sb4Te7 & N-doped Ge1Sb4Te7 thin films (Yonsei U.)
• 9.2 Effect of Indium in SbTe on PCM Characteristics (Yonsei U.)
• 9.3 Properties of Te-less, Sb-Rich GaSb PCM (Nat. Tsing Hua Univ.)
• 9.4 PCM Electrical Characteristics Using Ga3Te2Sb12 & Ge2Sb2Te5(Nat. Tshing Hua U)
• 9.5 Carbon Nanotube Heaters with < 5 nm Diameter for GST PCM (Univ. of Illinois)
• 9.6 Evolution of Band Gap & Fermi Level with Annealing Temp of Ge1Sb2Te4(Aachen U)
• 9.7 A GeTe and Sb7Te3 SuperLattice Structure PCM to reduce RESET Current(A*STAR)
• 9.8 Advantage of Ge21Sn10Sb15Te54 (GSST) for MLC PCM (ITRI)
• 9.9 Study of Ge15Te83Si2 for Use in Phase Change Memories (Indian Institute of Science)
• 9.10 Phase-Change Memories Using Gallium-Doped Indium Oxide (National Taiwan Univ.)
• 9.11 PC-RAM using GeTe and In2Se3 Nanowires (Ames Res. Ctr., NASA)
• 9.12 PCM Made from InGaO (Nat. Taiwan Univ.)
• 9.13 Investigation of PCM based on Ga2Sb8Te1. (Shanghai Jiaotong Univ)

10.0 Multi-Level Phase Change Memory Operation

• 10.1 Multi-Level Storage in Double-Layered TiSiN/GeSbTe PCM
• 10.2 Methodologies for Multilevel Programming of PCM (Univ. of Pavia)
• 10.3 Parallel Multi-Confined PCM Cell for Multi-Level Operation
• 10.4 Drift During ML Storage Dependence on Amorphous Capacitor Thickness(U. of Pavia)
• 10.5 90 nm 128-Mb PCM with BJT and Multilevel Storage (Numonyx, STM, U. of Pavia)
• 10.6 Effect of N-Type Doping on Power and Multi-Level Properties in a PCM (Gunma U.)
• 10.7 Multi-Level Lateral PCM Using a Top Heater (Gunma Univ.)
• 10.8 Two Bit, Four Level PCM Cell Operation (Samsung)
• 10.9 256Mb Multilevel Cell PCM Technology and Operation (STMicroelectronics)

11.0 Modeling of Phase Change Memory

• 11.1Amorphous GST Model for RESET Readout I Distribution(Numonyx, Polit.Milano)
• 11.2 Model of the Erase Operation in Phase Change Memories (U. of Ferrara)
• 11.3 Conduction Model for Amorphous Phase of PCM (Politecnico di Milano)
• 11.4 Model of Electrical Conduction Due to Hopping in Amorphous GST (U. of Bologna)
• 11.5 Modeling of Amorphous State in Mushroom Type PCM Devices (IBM, Macronix)
• 11.6 System Level Modeling of The Phase Change RAM Penn. State Univ.)
• 11.7 Transport Model for Amorphous PCM(U.of Bologna,U.of Modena&Reggio Emilia)
• 11.8 SPICE-like Statistical Model of Bit Distributions in PCN (Numonyx, Univ. of Pavia)
• 11.9 Threshold Switching as a Requirement for NV PCM Devices (Aachen Univ.)
• 11.10 Modeling Approaches for PCM (Politecnico di Milano)
• 11.11 Model for MLC PCM (University of Pavia)
• 11.12 Temperature Distribution Model in Cylindrical NanoWire PCM (U. of Illinois)
• 11.13 SPICE macromodel of Phase Change Memory (National Taiwan University)
• 11.14 Unified Field Induced Nucleation Model to Describe PCM Switching(Univ.of Toledo)
• 11.15 Model for use in SPICE Simulation of PCM Circuits (U. of Sci & Tech. Hong Kong)
• 11.16 Model for Write Speed in MLC Phase Change Memory (Nat. Ilan University)
• 11.17 Phase Transition Model and Resulting Simulations (Peking University)
• 11.18 PCM Model Characterizing Effects of Threshold Switching (Politecnico di Milano)
• 11.19 3-D Finite Element Model of Thermal Effects in PCM Cell Design(Chi.Acad.of Sci.)
• 11.20 PCM Model in Verilog-A (Hong Kong Univ. of Sc. and Tech.)
• 11.21 Modeling the Threshold Switching Curve in a PCM (Peking Univ.)
• 11.22 TCAD Model for PCM (Synopsys)
• 11.23 Process-Aware Compact Model of PC-RAM (Samsung)
• 11.24 Finite Element Simulator Model of PCM Cell (U. of Pavia)
• 11.25 Modeling Max. Temperature of a GST PCM (Nat. Chiao Tung Univ.)
• 11.26 Model for PCM Using Crystallization& Amorphization Rate Equations (Renesas)
• 11.27 HSPICE Model for PCM Thermal and Electrical Conductivities (Nat. Ilan Univ.)
• 11.28 Thermal Model of GST Based PCM (Stanford Univ.)
• 11.29 Model for Amorphous Drift Coefficient of PCM (ST Microelectronics)
• 11.30 Modeling a Confined Cell PCM (Stanford University)

12.0 Reliability, Test and Characterization of Phase Change Memory Devices

• 12.1 Impact of Thermal Disturbance on PCM Reliability(Stanford U&NXP-TSMCRes.Ctr)
• 12.2 Effect of BJT-PCM Scaling on Reliability and Functionality to 16 nm (Numonyx)
• 12.3 Lowered Endurance at High Temperatures of Ge2Sb2Te5 (Numonyx)
• 12.4 Effect of PCM Technology Scaling on Program and Read (U. of Pavia)
• 12.5 Effect of Parasitic Capacitance on Programming Performance of PCM (A*STAR)
• 12.6 Thermal Boundary Resistance Measurements for PCM Devices (Stanford U.)
• 12.7 Overview of PCM Reliability (Numonyx)
• 12.8 Metal - GST Interface Characterization (Nat. Univ. of Singapore)
• 12.9 Characterizing a PCM Cell Programmed to Intermediate Resistance Levels (IBM)
• 12.10 Variation of PCM Device Parameters with Ambient Temperature (KIST)
• 12.11 Threshold Current Densities in PCM (Onyx International)
• 12.12 Crystallization Time of Various Compositions of Ge-Te PC Materials(IBM, Macronix)
• 12.13 Effect of ESD on PCM Structures (Univ. of Padova)
• 12.14 Effect of RESET Parameters on the Final RESET State (IMEC, NXP-TSMC)
• 12.15 Electromigration in Molten/Crystalline GST Under High Field (Seoul Nat. Univ.)
• 12.16Crystal growth rate of GeTe PCM Devices and Switchable Volume (Aachen Univ.)
• 12.17SET Stuck Failure in GST Phase Change Memory (KIST)
• 12.18Doping to Reduce Failure from Voids in GST Programming Volume(IBM, Macronix)
• 12.19Phase Separation in Ge2Sb2Te5 Due to High Electrical Stress (Samsung)
• 12.20 Data Retention Improvement at High Temp. Using GeTe (CEA/LETI-Minatec)
• 12.21 Various Programming Techniques for Writing a MLC PCM (Nat. Ilan, Univ.)
• 12.22ndurance of an Integrated Phase Change Line Cell (IMEC)
• 12.23Low Power Test of PCM Devices (Cheng Kung University)
• 12.24Effect of Ion Radiation on PCM with MOSFET and BJT Selectors (U. di Padova)
• 12.25Effect of Cell Geometry on the RESET Process (U. of Pavia)
• 12.26 Temperature Dependence of PCM Programmed Resistance States (U. of Pavia)
• 12.27 Ionizing 8-MeV Radiation Dose Effects on a 4-Mb PCM (U. of Padova)
• 12.28Reliability and Radiation Testing of a PCM Test Chip (Boise State U.)
• 12.29Investigation of Long Cycled PCM Including a Refresh Method (KAIST)
• 12.30Determination of GST Crystallization Activation Energy(STMicro, Polit.di Milano)

13.0 Design and Circuits for Phase Change Memories

• 13.1 4-Mb 90 nm PCM Macro with 1.2V 12 ns Read and 1/MB/s Write
• 13.2 Design of 45 nm 1 Gb PCM (Numonyx)
• 13.3 Design Methodology for A PC-RAM Array (Penn State University)
• 13.4 Slow Quench Pulse Shaper for SET Mode for PC-RAM (Penn State Univ.)
• 13.5 Using DACs to Replace Write Drivers in PCM Circuits (Boise State Univ.)
• 13.6 Four Terminal Phase Change Programmable Switch (ETRI)
• 13.7 Program Circuit for a 90 nm 4-Mb Embedded PCM (STMicroelectronics)

14.0 Processes for the PC-RAM Cell

• 14.1 Making PCM in the Univ. Environment Using Foundry FEOL CMOS (Boise State U)
• 14.2 GeSbTe Epitaxy on GaSb(001) Grown at Low Temperature(Inst. for Solid State Elec.)
• 14.3 Ultimate Size Limits for PCM (TRIZ Experts)
• 14.4 Characteristics for Scaling the PCM (NXP-TSMC)
• 14.5 Etching a sub-100 nm PCM Cell using UV NanoImprint Litho(Nano-Tech Lab)
• 14.6 Effect of Various Dopants in Phase Change Memories
  • 14.6.1 Role of Nitrogen During Crystallization of Sb-Rich Phase Change Materials (KIST)
  • 14.6.2 Etching Characteristics of Nitrogen Doped GST(IBM)

15.0 Techniques to Improve PCM System Level Reliability

• 15.1 Using "Read-Modify-Write" to Improve Write Endurance (Univ. of Pittsburgh)
• 15.2 Technique to Improve Cell-Based Non-Uniformity of Writes in a System (IBM)
• 15.3 Implications of Process Variations in PCM System Design (Univ. of Florida)

16.0 Developers and Vendors of Phase Change and Resistance RAMs

• 16.1 BAE Systems (Phase Change RAM)
• 16.2 Elpida and UMC
• 16.3 IBM, Macronix,
• 16.4 IMEC
• 16.5 Intel
• 16.6 ITRI
• 16.7 Macronix/IBM
• 16.8 Numonyx (Intel and STMicroelectronics) / Micron
• 16.9 NXP and TSMC
• 16.10 Ovonyx
• 16.11 Renesas (Hitachi)
• 16.12 Samsung
• 16.13 ST Microelectronics

Bibliography

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