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A Memory Strategies Focus Report

Phase Change Memory Trends
March 2011

Phase change memories are expected to be used in disk caches in servers, in hybrid non-volatile memory caches and Flash file systems. They can replace NOR flash in code applications. They are potentially useful as memory in portable smart systems, in industrial systems and smart metering.

Several companies have shown integrated process technologies for phase change memory in technologies ranging from 90 nm to 45 nm. Since the PCM is a new technology there are several issues still being addressed such as: resistance drift in the amorphous state in multilevel cells, thermal program disturb of neighboring cells in the RESET state, stability of the PCM at high temperatures using GeTe and inclusions for improved temperature stability, endurance failures due to electromigration and voids in the PCM element, data loss from the amorphous state, reducing write current, and oscillatory behavior due to noise in the amorphous state. Phase Change memories using BJT access devices have been described as have PCM in cross-point cells with scaled diode switches. A number of novel material combinations are being explored for PCM including different percentages of Ge Sb and Te, and the use of GeTe in a PCM cell for high temperature improvement.

Multilevel phase change memories have been explored for effects such as resistance drift and effect of doping and type of select device. A significant amount of modeling and reliability characterization is still ongoing for PCM. Designs with various circuits for the PCM have been discussed. Several advanced processes such as superlattices, alloys and epitaxies have been shown. System level reliability was addressed Vendors and developers are noted in the last section.

115+ pages.

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Table of Contents - Phase Change Memory Trends , March 2011

1.0 Overview of Phase Change Memory and Its Characteristics

2.0 Applications For Phase Change Memory

• 2.1 Main Memory System Using PC-RAM (Penn State University)

• 2.2 Computing Platforms

• 2.3 Using Phase-Change Memory in Caches

  • 2.3.1 A Low Power, High Endurance PCM Cache

  • 2.3.2 Using PCM in a as Disk Cache in Servers (University of Michigan)

  • 2.3.3 Hybrid Non-Volatile Memory Caches including MRAM, PC-RAM and SRAM(IBM)

• 2.4 Flash File System Based on Hybrid Architecture of PCM and NAND(KAIST)

• 2.5 Including PCM in Stacked TSV DRAM and MPU Systems (Univ. of Florida)

• 2.6 PC-RAM as NOR Flash Memory Replacement

• 2.7 Air, Military and Space Applications (BAE Systems)

• 2.8 Automotive and Consumer Applications (CEA/LETI-Minatec)

• 2.9 PC-RAM and DRAM Hybrid in Main Memory Architecture in Computing Systems

• 2.10 Low Power Smart Portable Handheld Systems

• 2.11 Industrial and Embedded Applications

• 2.12 Solid State Storage Subsystems

• 2.13 Set-Top Boxes

• 2.14 Smart Metering
  

3.0 Technology Overview for the Phase Change Memory

• 3.1 Basic Operation of Phase Change Memory
• 3.2 Cell Sizes vs. Technology for Phase Change Memory
• 3.3 Overview of PCM Technology Roadmap
• 3.4 PCM Scaling Trends
• 3.5 Scaling Behavior of GST Technology
  

4.0 Integrated Process Technologies For Phase Change Memory

• 4.1 4-Mb 1T1R GST ePCM in 90 nm CMOS (STMicro, Numonyx)

• 4.2 Embedded PCRAM in 65 nm CMOS Technology (NXP-TSMC)

• 4.3 Fast sub-20 nm Dash Confined Cell PRAM (Samsung)

• 4.4 1-Gb PCM in 45 nm CMOS Technology (Numonyx)

• 4.5 Integrated PCM Process Module Embedded in 90 nm 6ML CMOS (STM, Numonyx)

• 4.6 60 nm 512-Mb PCM Technology (Samsung)
  

5.0 Issues for Phase Change Memory

• 5.1 Resistance Drift Due to Structural Relaxation in Amorphous State

  • 5.1.1 Effect of Resistance Drift on Multi-Level PCM Design

  • 5.1.2 Time-Aware Fault Tolerance Reliability of MCL PCM with Resistance Drift (Marvell)

  • 5.1.3 Time Aware Memory Sensing for Resistance Drift Issues (Rensselaer Institute)

  • 5.1.4 Characterization of Resistance Drift in Amorphous GST (U. of Pennsylvania)

  • 5.1.5 Structural Relaxation in the Amorphous State of a MLC PCM (Polit. di Milano)

  • 5.1.6 Study of Resistance Drift and Its Dependence on Temperature (Politecnico di Milano)

  • 5.1.7 Characterization of Structural Relaxation in Amorphous PCMs (Politech. di Milano)

• 5.2 Thermal Programming Disturb

  • 5.2.1 Thermal Programming Disturb of Neighboring Cell in RESET State (Hynix)

  • 5.2.2 Impact of Thermal Disturbance on PCM Reliability(Stanford U&NXP-TSMCRes.Ctr)

• 5.3 Stability of PCM at High Temperatures

  • 5.3.1 GST PCM Alloys with SiO2 Inclusions for Improved Temperature Stability(Ovonyx)

  • 5.3.2. PCM with High Temperature Endurance (Nat. Tsing Hua U., Feng Chia U.)

  • 5.3.3 Stability at Varying Temperature of PCM Using Ge doped SbTe (KIST)

  • 5.3.4 Refresh to improve Endurance at High Temperatures of Ge2Sb2Te5 (Numonyx)

  • 5.3.5 Variation of PCM Device Parameters with Ambient Temperature (KIST)

• 5.4 Endurance Failure Caused by Electromigration During SET.

  • 5.4.1 Endurance Failure from Electromigration in Asymmetric GST PCM (Macronix, IBM)

  • 5.4.2 Voltage Polarity Effects in GST PCM (IBM)

  • 5.4.3 Electromigration in Molten/Crystalline GST Under High Field (Seoul Nat. Univ.)

  • 5.4.4 SET Stuck Failure in GST Phase Change Memory (KIST)

  • 5.4.5 Doping to Reduce Void Failure in GST Programming Volume (IBM, Macronix)

  • 5.4.6 Phase Separation in Ge2Sb2Te5 Due to High Electrical Stress (Samsung)

• 5.5 Data Loss from the Amorphous (RESET) State of the Phase Change Memory

  • 5.5.1 Multiple Amorphous States for Undoped Ge15Sb85 Bridge PCM (Aachen Univ.)

  • 5.5.2 Observations of Slow Quenching Crystallization Behavior(Samsung, U. of Texas)

  • 5.5.3 Parasitic Crystal Path in SET Related to Anomalous Tail Bits in RESET(UdiFerrara)

• 5.6 Reducing Write Current in Phase Change Memory

  • 5.6.1 Reducing Thermal Conductivity in PCM to Reduce Programming Current (Samsung)

  • 5.6.2 Lower RESET Current Using TiO2 Insert in Confined GST PCM (U. Khon Kaen)

• 5.7 Oscillatory Behavior (Noise Fluctuations) in an Amorphous State PCM

  • 5.7.1 Current Fluctuation Effects of Scaled PCM (Politecnico di Milano)

  • 5.7.2 Low Frequency Noise in Amorphous State of PCM (Numonyx)

  • 5.7.3 Relaxation Oscillation Study of GST PCM Devices (University of Toledo)

• 5.8 Dynamic Resistance of the PCM Cell

  • 5.8.1 Measurements of Dynamic Resistance of the PCM Cell (IBM, Macronix)

6.0 Characterization of the SET Operation in PC Memories

• 6.1 Effect of Cycling on the SET State of a high capacity PCM (D. degli Studi di Ferrara)
• 6.2 Analysis of PCM Transient Current Waveform During Crystallization (A*STAR)
  
• 6.3 MicroStructural Evolution of Slow Quenching Crystallization (U. of Texas, Samsung)
  

7.0 Phase Change Memory Using BJT Access Devices

• 7.1 Effect of BJT-PCM Scaling on Reliability and Functionality to 16 nm (Numonyx)
• 7.2 Comparison of MOS and BJT Selectors for PCM (Numonyx)
• 7.3 Two Bipolar Transistor and Two PC Device Cell Structure PCM (Fudan U.)
• 7.4 Vertical BJT Access Device in 180 nm Technology (IBM, Macronix)
• 7.5 90 nm 128-Mb PCM with BJT and Multilevel Storage (Numonyx, STM, U. of Pavia)
  

8.0 Phase Change Memory Cross-Point Cells with Scaled Two-Terminal Switches

• 8.1 MIEC Access Devices for 3D Stacked Crosspoint Arrays (IBM)
• 8.2 Stacking PCM in Cross-Point Array with Ovonic Threshold Switch (Intel, Numonyx)
• 8.3 Cross-Point PCM Using Polysilicon Selection Diode (Hitachi)
• 8.4 Cross-Point Array Using p-GST to n-Si Heterojunction Diodes (Fudan Univ.)
• 8.5 Circuit and Design of Scaled Diode Switch PCM (Rensselaer Polytechnical Institute)
  

9.0 Novel Materials Combinations for Phase Change Memory Cells

• 9.1 Super-Lattice Dielectric of GST and SiO2 for PCM Dielectric (NUS)

• 9.2 Characteristics of PCM Devices Made with MOCVD GST 325 alloy (Ovonyx)

• 9.3 Using Silicides for the Bottom Electrode/Heater of a Phase Change Memory (NUS)

• 9.4 Characteristics of (InTe)x(GeTe) Thin Films for PRAM Applications(Chonnam Nat.U)

• 9.5 Performance Improvement of a CeO2 Buffer Layer in a PCM Cell (Tongji U.)

• 9.6 Thermal Conductivity of Ge1Sb4Te7 & N-doped Ge1Sb4Te7 thin films (Yonsei U.)

• 9.7 Effect of Indium in SbTe on PCM Characteristics (Yonsei U.)

• 9.8 PCM Electrical Characteristics Using Ga3Te2Sb12 & Ge2Sb2Te5(Nat. Tshing Hua U)

• 9.9 Properties of Te-less, Sb-Rich GaSb PCM (Nat. Tsing Hua Univ.)

• 9.10 Carbon Nanotube Heaters with < 5 nm Diameter for GST PCM (Univ. of Illinois)

• 9.11 Evolution of Band Gap & Fermi Level with Annealing Temp of Ge1Sb2Te4(AachenU)

• 9.12 Advantage of Ge21Sn10Sb15Te54 (GSST) for MLC PCM (ITRI)

• 9.13 Study of Ge15Te83Si2 for Use in Phase Change Memories (Indian Institute of Science)

• 9.14 Phase-Change Memories Using Gallium-Doped Indium Oxide (National Taiwan U.)

• 9.15 Using GeTe Materials in Phase Change Memory

  • 9.15.1 N-Doped GeTe for Performance in ePCM(CEA-LETI,STM,LTM-CNRS,dStudidiPavia)

  • 9.15.2 Electrical Behavior of GeTe PCM Cell (CEA-LETI, STMicroelectronics)

  • 9.15.3 Investigation of Properties of GeTeC Alloy for Using in PCM (CEA-LETI MINATEC)

  • 9.15.4 Crystal growth rate of GeTe PCM Devices and Switchable Volume (Aachen Univ.)

  • 9.15.5 A GeTe and Sb7Te3 SuperLattice Structure PCM to reduce RESET Current(A*STAR)

  • 9.15.6 Data Retention Improvement at High Temp. Using GeTe (CEA/LETI-Minatec)
    

10.0 Multi-Level Phase Change Memory Operation

• 10.1 Analysis of Noise in Multi-bit PCM (IBM)

• 10.2 Multilevel PCM Using Stacked CVD GET and ALD TiO2 thin Films (Seoul Nat. U.)

• 10.3 45 nm 2-bit/cell MLC PRAM (Samsung)

• 10.4 Effect of Resistance Drift on Multi-Level PCM Design (Nat. Ilan U.)

• 10.5 Multilayer Multilevel Lateral PCM Using N-doped Sb70Te20 (A*STAR)

• 10.6 Multi-Level Storage in Double-Layered TiSiN/GeSbTe PCM (Gunma Univ.)

• 10.7 Characterizing a PCM Cell Programmed to Intermediate Resistance Levels (IBM)

• 10.8 Methodologies for Multilevel Programming of PCM (Univ. of Pavia)

• 10.9 Parallel Multi-Confined PCM Cell for Multi-Level Operation (Samsung)

• 10.10 Drift During ML Storage Dependence on Amorphous Capacitor Thickness(Uof Pavia)

• 10.11 90 nm 128-Mb PCM with BJT and Multilevel Storage (Numonyx, STM, U. of Pavia)

• 10.12 Effect of N-Type Doping on Power and Multi-Level Properties in a PCM (Gunma U.)
  

11.0 Modeling of Phase Change Memory

• 11.1 Modeling of PCM Resistance Temp. & Time Dependency(Polit. di Milano, IFN-CNR)

• 11.2 Transient Model for Threshold Switching of Amorphous PCM (Politecnico di Milano)

• 11.3 Amorphous GST Model for RESET Readout I Distribution(Numonyx, Polit.Milano)

• 11.4 Model of the Erase Operation in Phase Change Memories (Univ. of Ferrara)

• 11.5 Conduction Model for Amorphous Phase of PCM (Politecnico di Milano)

• 11.6 Model of Electrical Conduction Due to Hopping in Amorphous GST (U. of Bologna)

• 11.7 Modeling of Amorphous State in Mushroom Type PCM Devices (IBM, Macronix)

• 11.8 System Level Modeling of The Phase Change RAM (Penn State Univ.)

• 11.9 Transport Model for Amorphous PCM(U.of Bologna,U.of Modena&Reggio Emilia)

• 11.10 SPICE-like Statistical Model of Bit Distributions in PCN (Numonyx, Univ. of Pavia)

• 11.11 Threshold Switching as a Requirement for NV PCM Devices (Aachen Univ.)

• 11.12 Modeling Approaches for PCM (Politecnico di Milano)

• 11.13 Model for MLC PCM (University of Pavia)

• 11.14 Temperature Distribution Model in Cylindrical NanoWire PCM (U. of Illinois)

• 11.15 SPICE macromodel of Phase Change Memory (National Taiwan University)

• 11.16 Unified Field Induced Nucleation Model to Describe PCM Switching(Univ.of Toledo)

• 11.17 Model for use in SPICE Simulation of PCM Circuits (U. of Sci & Tech. Hong Kong)

• 11.18 Model for Write Speed in MLC Phase Change Memory (Nat. Ilan University)

• 11.19 Phase Transition Model and Resulting Simulations (Peking University)
  

12.0 Reliability, Test and Characterization of Phase Change Memory Devices

• 12.1 Activation Energy of Crystal Growth in Amorphous Chalcogenide(IMEC, NXP, TSMC)
• 12.2 Study of phase transition behaviour of GST thin Films for PCRAM (IBM, Macronix)
• 12.3 Thermoelectric Heating During Programming of PC Memory Cells (Samsung)
• 12.4 Effect of PCM Technology Scaling on Program and Read (U. of Pavia)
• 12.5 Effect of Parasitic Capacitance on Programming Performance of PCM (A*STAR)
• 12.6 Thermal Boundary Resistance Measurements for PCM Devices (Stanford U.)
• 12.7 Overview of PCM Reliability (Numonyx)
• 12.8 Metal - GST Interface Characterization (Nat. Univ. of Singapore)
• 12.9 Crystallization Time of Various Compositions of Ge-Te PC Materials(IBM, Macronix)
• 12.10 Threshold Current Densities in PCM (Onyx International)
• 12.11 Effect of ESD on PCM Structures (Univ. of Padova)
• 12.12 Effect of RESET Parameters on the Final RESET State (IMEC, NXP-TSMC)
• 12.13 Various Programming Techniques for Writing a MLC PCM (Nat. Ilan, Univ.)
• 12.14 Endurance of an Integrated Phase Change Line Cell (IMEC)
  

13.0 Design and Circuits for Phase Change Memories

• 13.1 58 nm 1.8 V 1-Gb PRAM with 6.34 MB/s Program Bandwidth (Samsung)
• 13.2 4-Mb 90 nm PCM Macro with 1.2V 12 ns Read and 1/MB/s Write(STM, Numonyx)
• 13.3 Design of 45 nm 1 Gb PCM (Numonyx)
• 13.4 Design Methodology for A PC-RAM Array (Penn State University)
• 13.5 Slow Quench Pulse Shaper for SET Mode for PC-RAM (Penn State Univ.)
• 13.6 Using DACs to Replace Write Drivers in PCM Circuits (Boise State Univ.)
• 13.7 Four Terminal Phase Change Programmable Switch (ETRI)
  

14.0 Processes for the PC-RAM Cell

• 14.1 Superlattice Phase Change Memory to Reduce Switching Energy (AIST)
• 14.2 Solid State Alloying to Form Phase-Change Memory (Hanbat National Univ.)
• 14.3 Making PCM in the Univ. Environment Using Foundry FEOL CMOS (Boise State U)
• 14.4 GeSbTe Epitaxy on GaSb(001) Grown at Low Temperature(Inst. for Solid State Elec.)
• 14.5 Role of Nitrogen During Crystallization of Sb-Rich Phase Change Materials (KIST)
  

15.0 Techniques to Improve PCM System Level Reliability

• 15.1 System Architecture to Reduce Write Internsity in PCM (Penn. State U.)
• 15.2 In-System Programming of PCM After Surface Mount Process (Micron)
• 15.3 Using "Read-Modify-Write" to Improve Write Endurance (Univ. of Pittsburgh)
• 15.4 Technique to Improve Cell-Based Non-Uniformity of Writes in a System (IBM)
• 15.5 Implications of Process Variations in PCM System Design (Univ. of Florida)
• 15.6 System Level Modeling for Scaling of PC-RAM (Penn State Univ.)
  

16.0 Labs, Developers and Vendors of Phase Change and Resistance RAMs

• 16.1 A*STAR
• 16.2 CEA-LETI / MINATEC
• 16.3 ETRI
• 16.4 Hitachi
• 16.5 Hynix
• 16.6 IMEC
• 16.7 Intel
• 16.8 ITRI
• 16.9 KAIST
• 16.10 KIST
• 16.11 Macronix/IBM
• 16.12 Numonyx (Intel and STMicroelectronics) / Micron
• 16.13 NXP and TSMC
• 16.14 Ovonyx
• 16.15 Samsung
• 16.16 ST Microelectronics

Bibliography

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