MEMORY STRATEGIES INTERNATIONAL Semiconductor Memory Services
| Home | Reports | Seminars | Consulting | Contact Us | About Us | Site Map | Links |

Contents | Purchase

A Memory Strategies Focus Report

Resistance RAM Technology and Development , July 2011

(Applications, Technology, Modeling, Simulation, Reliability)

In the past year the resistance RAMs have moved from research to the development stage. A few technologies - TiO, HfO2, NiO, Cu doped and CuO have come to predominate although work continues by several major companies in other materials. A significant amount of modeling has been done both for basic understanding of the ReRAM switching mechanism and preparatory modeling for functional devices and circuitry. A better understanding of the switching mechanism of the metal oxide ReRAM has developed and unified models that bring together the various experimental observations have been discussed. ReRAM and CB-RAM macros have been shown and support circuitry for ReRAM operation have been discussed including cross-bar architectures. Real life applications are mentioned more often. This report discusses these various technical works and also the potential vendors who are engaged in development efforts on the ReRAM and conductive bridge (CB) RAM.

100+ pages.

Overview | Purchase

Table of Contents - Resistance RAM Technology and Development, July 2011

Executive Summary

1.0 Overview of Resistance RAMs

2.0 Applications For Resistive RAMs

• 2.1 8T2R Non-volatile Rnv8TSRAM for Low Power Mobile Applications
• 2.2 Storage Class Applications for Resistive RAMS
• 2.2.1 Overview of Storage Class Memory
• 2.3 SSD Applications for ReRAM
• 2.5 ReRAM for Flexible Electronics
• 2.5.1 NV RRAM Memory of Flexible Plastic Substrate (NTHU, NCTU)
• 2.5.2 ReRAM MIM Based on Graphene Oxide for Flexible Electronics (KAIST, ETRI)
• 2.6 Radiation Resistant RRAMs for Air, Space and Nuclear Applications

3.0 Embedded Memory in Logic Applications

• 3.1 The Challenge of Portable Mobile Applications
• 3.2 CMOS FPGA and Routing Switches Made with RRAM Devices
• 3.3 System-on-Chip Using ReRAM and 1T-DRAM Unified RAM for Embedded Memory
• 3.4 ReRAM Embedded in Interconnects for Programmable Logic

4.0 Overview of Metal Oxide Memory Elements

5.0 Technical Issues and Mechanisms of Various RRAMs

• 5.1 Technical Issues and Mechanisms of Zirconium (Zr) Metal Oxide Memories.
  • 5.1.1 Ti/ZrO2/Pt/Ti 1T1R RRAM with Multilevel LRS (NCTU, Winbond)
  • 5.1.2 Effects of RTA on Oxygen Annealed SrZrO3 RRAM (Winbond, NCTU)
  • 5.1.3 ZrO2 Crossbar RRAM built on a foundry platform substrate (Chin. Acad. Of Sci)
  • 5.1.4 Metallic Ion Doping Effect on Switching Uniformity in ZrO2 RRAMs (Peking Univ.)
  • 5.1.5 Effect of Vanadium Doping of SrZrO3 Film on ReRAM Characteristics(NCTU)
  • 5.1.6 Electrical Properties and Structures of ZrTiO4 Thin Film for ReRAM(Nat.United .Univ.)
• 5.2 Technical Issues and Mechanisms of Nickel (Ni) Metal Oxide Memories
  • 5.2.2 Nickel Nanocrystals in TiO2 Film in RRAMs (IIT India)
  • 5.2.3 Scaling Analysis of NiO RRAM (Politecnico di Milano)
  • 5.2.4 Model for Switching Phenomena in Unipolar NiO-based RRAM (Stanford U.)
  • 5.2.5 Resistive Switching Characteristics of Al-inserted NiO RRAM (Seoul Nat. Univ.)
  • 5.2.6 RESET-SET Instability in NiO ReRAM Cross-Bar Array (Politechnico di Milano)
  • 5.2.7 Unipolar NiOx ReRAM Pulse Programming Instabilities (Samsung)
  • 5.2.8 Irregular Resistive Switching in NiO ReRAM Cross-Bar Structure (Seoul Nat. Univ.)
  • 5.2.9 Data Retention & RESET Current Trade-Off in NiO RRAMs (Politech. di Milano)
  • 5.2.10 10 uA Ireset in Diode Crossbar RRAM (Polit. Di Milano, IUNET, IMM, CNR, IMEC)
  • 5.2.11 Vertical Cross-Point NiO Transition Metal Oxide RRAM (Samsung)
  • 5.2.12 Confined TMO NiO RRAM Cell for Improved Uniformity ( Stanford Univ.)
  • 5.2.13 Characterization of NiO RRAM in Low Resistance State (Politechnico di Milano)
  • 5.2.14 Model for Physical Switching Mechanism in NiO Memory (Politechnico di Milano)
• 5.3 Technical Issues and Mechanisms of Titanium (Ti) Metal Oxide Memories
  • 5.3.1 Multibit TiOx ReRAM by Controlling Schottky Barrier Height (Gwangju Inst.S&T)
  • 5.3.2 Bipolar 54 nm Node TiN/Ti/TiOx/TiN ReRAM in 1T1R Arrays (Hynix)
  • 5.3.3 Oxygen Injection for Bipolar Forming-Free TiN/TiOx/TiN RRAM (Nanya)
  • 5.3.4 180 nm CMOS TiO2-SiO2 eRRAM Cell (NCTU, Nat. Nano Dev. Lab., Fu Jen U)
  • 5.3.5 Variable Voltage SET/RESET Operation to Improve Switching Uniformity (Gwangju)
  • 5.3.6 Impact of Oxygen Vacancy Ordering on CF Formation in TiO2 RRAM (Stanford U.)
  • 5.3.7 90 nm CMOS Compatible1T1R TiN/TiON/Si Contact RRAM (NTHU, TSMC)
  • 5.3.8 Low Power 10 nm AlOx/TiOx Bipolar ReRAM (Samsung, KAIST, SEMATECH)
  • 5.3.9 Model of Negative Resistance and Switching Behavior in TiOx RRAM (Tsinghua U.)
  • 5.3.10 Ir/TiO2/Ir ReRAM with Inserted Al Layer (Seoul Nat. Univ.)
  • 5.3.11 90 nm TiN/TiON RRAM Cell in CMOS Logic Technology (Nat. Tsing-Hua U, TSMC)
  • 5.3.12 Memristor Pt/TiO2-x/Ti Cross-Bar Memory Devices
  • 5.3.12.1 Read and Write Model of Cross-Bar Pt/TiO2-x/Ti Memristor Memory (HP Labs)
• 5.4 ReRAM Stacks Using Ta2O5 and Thin TiO2 (NEC)
  • 5.4.1 Memory State Dependence of RTN of Ta2O5/TiO2 ReRAM (Renesas, NEC)
  • 5.4.2 TaOx/TiN RRAM for Multi-Level Cell Applications (Peking Univ.)
  • 5.4.3 Improving Operating Margin for Ta2O5/Plasma oxidized TiO2 1T1R Cell (NEC)
  • 5.4.4 Controlling Resistance in Multilevel and Low Voltage Ti2O5/TiO2 ReRAM (NEC)
  • 5.4.5 RTN and Retention of Bottom Electrode of Ta2O5/TiO2 ReRAM Stack (NEC)
  • 5.4.6 Effect of TiO2 ReRAM Stack Asymmetry on Read Disturb Immunity (NEC)
• 5.5 Circuits, Technical Issues and Mechanisms of HfO2 Metal Oxide Memories
  • 5.5.1 RRAM in Pure Vo Regime using HfSiON bilayer stack (NanyangTU,A*STAR,IMEC)
  • 5.5.2 Unipolar Switching of Hi/HfO2/TiN RRAM (IMEC, KU Leuven)
  • 5.5.3 Multilayer Forming-Free HfOx RRAM with Improved Uniformity (A*STAR)
  • 5.5.4 Physical Mechanism Description of HfO2-based Bipolar RRAM (NTU, ITRI)
  • 5.5.5 Process Compatible Ni/Ox Anode for Unipolar HfOx RRAM (ITRI,NTHU,MingShinU)
  • 5.5.6 High Yield Ni/HfOx/n+ Si RRAM Cross-Bar+ Si Diode (Nanyang,NUS Soitec,Fudan)
  • 5.5.7 Low Energy Ni/GeOx/HfON/TaN RRAM (NTHU)
  • 5.5.8 New Operation Method for HfOx-based RRAM (Peking U., and STate U. of NY)
  • 5.5.9 Characteristics of 50 nm Ti/HfOx Pillar RRAM with Si3N4 Encapsulation(ITRI)
  • 5.5.10 4Mb HfO2 ReRAM Macro with 7.2ns/160 ns SLC/MLC Capability(ITRI, NTHU, NCU)
  • 5.5.11 Improved Performance in HfO2 RRAM Using Implanted Gd Doping (Peking U.)
  • 5.5.12 4F2 CMOS Cross-Bar HfO2 ReRAM with Vertical BJT Access(NTHU, ITRI)
  • 5.5.13 CF & HfO2 RRAM Switching (SEMATECH, DISMI, UCLondon, U.A.Barcelona)
  • 5.5.14 Switching of HfOx and AlOx based RRAM with 2-bit storage (Stanford U., IBM)
  • 5.5.15 180 nm Fully Integrated 1-Kbit Array HfOx-based RRAM (NTHU)
  • 5.5.16 Voltage Pulse Dependent Resistive Switching in HfO2 Based RRAM (Peking U.)
  • 5.5.17 Study of Switching Characteristics of HfO2 ReRAM (Hynix)
  • 5.5.18 Pillar Structured Ti/HfO2 ReRAM (ITRI)
  • 5.5.19 Anodic Interface Layers in Unipolar Switching of HfO2 ReRAM (IMEC, KathULeuv.)
  • 5.5.20 1Kb HfO2 RRAM in 180 nm CMOS (ITRI, MingShin U., Tsing Hua U.)
  • 5.5.21 Uniformity Improvement with Al-doped HfO2 ReRAM Materials(PekingU. and SUNY)
• 5.6 Technical Issues and Mechanisms of Cu doped and Cu Metal Oxide RRAM
  • 5.6.1 Effect of TE Materials on Switching of CaCu3Ti4O12 Films (TSMC, NDJU, NCTU)
  • 5.6.2 Effect of Top Electrode Material on CaCu3Ti4O12-based RRAM (Nat. Dong Hwa Univ.)
  • 5.6.3 CuAlO Interface in Switching of Al/CuxOCu RRAM (FudanU, Chin.Acad. of Sci.)
  • 5.6.4 Switching Mechanism of ZrO2 RRAM using Cu Doped ZrO2
  • 5.6.5 ZrO2 ReRAM with Cu NC Layer (Chinese Acad. of Sci., Anjui U., U. of Albany)
  • 5.6.6 Reliability Issues for CuxO-based RRAM (Fudan University)
  • 5.6.7 Switching Characteristics of Cu/Cu:HfO2/Pt Based ReRAM (Chin. Acad. Of Sci)
  • 5.6.8 Reducing Resistance Dispersion in CuxO ReRAM using a GST layer(Fudan Univ.)
  • 5.6.9 Unipolar Cu/TaOx ReRAM Using Electrode Engineering (Peking)
  • 5.6.10 Embedded CuxSiyO ReRAM in CMOS Logic (SMIC)
  • 5.6.11 Analysis of RRAM Structured as Cu/SixOyNz/W (Silicon Nano. Workshop)
  • 5.6.12 Filamentary Channel ReRAM with Cu Doped ZrO2 (Chinese Acad. Of Sci.)
  • 5.6.13 Copper Doped SrZrO3 and SrTiO3 (IBM Zurich)
  • 5.6.14 Copper Doped MoOx / GdOx Bilayer Films (Gwangju Inst. of Sci. & Tech.)
  • 5.6.15 Bistable Resistance Switching in CuO Thin Films (Pusan Nat. Univ.)
• 5.7 Technical Issues and Mechanisms of Tungsten (W) Metal Oxide Memories
  • 5.7.1 Switching Mechanism for WOx ReRAM (Macronix)
  • 5.7.2 Microstructure and Electrical Properties of Tungsten Oxide RRAMs (Macronix)
• 5.8 Technical Issues and Mechanisms of Aluminum Metal Oxide Memories
  • 5.8.1 Al2O3-based RRAM with Ru NC to Improve Memory Performance (Fudan U.)
  • 5.8.2 ALD Al2O3-Based RRAM with 1 uA RESET Current (Stanford U.)
  • 5.8.3 RRAM Using ALD Al2O3 for the Resistive Layer (Stanford)
  • 5.8.4 Unified Memory Resistance RAM Using Al2O3 Film (KAIST)
• 5.9 Technical Issues and Mechanisms of Gadolinium Oxide Memories
  • 5.9.1 Low Resistance State Stability for a Pt/Cu:MoOx/GdOx/Pt ReRAM Device (Gwangju)
  • 5.9.2 Bipolar Transparent RRAM using Gd2O3 (Chang Gung U.)
• 5.10 Technical Issues and Mechanisms of GeOx/SrTiO3 Memories
  • 5.10.1 Cross-Bar 4F2 ReRAM Using Ni/GeO/SrTiO/TaN (NTHU, NCTU)
  • 5.10.2 Bipolar GeOx/SrTiO3 low Energy RRAM (NTHU, NCTU)
• 5.11 Technical Issues and Mechanisms of Carbon-Based RRAM Memories
  • 5.11.1 Diamond-Like Carbon-Based Unipolar RRAM (Tsinghua U., Chinese Acad. of Sci.)
  • 5.11.2 Carbon RRAM with CNT Electrodes (Stanford U, Berkeley, HK U.Sci&Tech, HK Poly)
  • 5.11.3 ReRAM MIM Based on Graphene Oxide for Flexible Electronics (KAIST, ETRI)
  • 5.11.4 Resistive Switching of Carbon-Based Resistive Memory Cells ((Tshinghua Univ.)
• 5.12 Technical Issues and Mechanisms of G:ZnO, CoOx, CeOx Metal Oxide Memories
  • 5.12.1 Flexible Transparent ReRAM with Ga Doped ZnO (GZO)
  • 5.12.2 128Kbit CoOx RRAM Array Made in a Via(Sharp, NIAIST, ULVAC, KanazawaU.)
  • 5.12.3 Resistive Switching of CeOx Films (Peking Univ.)

6.0 Other Resistive Switching Materials

• 6.1 ZnO Nanowire RRAM ( Nat. Taiwan U., NTHU, Chung Yuan U., Purdue U.)
• 6.2 Electric Field Resistive Switching in Mott Insulators (U de Nantes, STMicroelectronics)
• 6.3 GAA/Nanowire Schottky Barrier FET ReRAM (Ecole Polytech Fed. De Lausanne
• 6.4 FeO and ZnFe Superlattices for ReRAM (Missouri Univ. of Sci. and Tech.)
• 6.5 Resistance Switching of Perovskite Oxide based Memory Device (Gwangju, Hynix)

7.0 Conductive Bridge/Programmable Metallization Cell Memories

• 7.1 Background of Conductive Bridge RAMs
• 7.2 Technical Issues of Programmable Metallization Cell Resistance Switches
• 7.2.1 4Mb CB-ReRAM Macro with New Read/Write Circuitry (Sony)
• 7.2.2 Model of RESET for Conductive Bridge ReRAM (Macronix)
• 7.2.3 Cu-GST Conductive Bridge RAM with TiTe Buffer Layer (Macronix)
• 7.2.4 PMC Memory for Storage Class Applications (Adesto Technologies)
• 7.2.5 Study of CB-RAM Resistance Ratio vs. Electrode Size (Samsung, Sejong U.)
• 7.2.6 Kinetic Study of PMC / CB-RAM (Politechnico di Milano, U. of Arizona)
• 7.2.7 Kinetics of Programming ML Cells in PMC Memory (Politechnico di Milano, ASU)

8.0 Simulation and Modeling of Metal Oxide Memory Cells

• 8.1 Atomistic Simulation of SET/RESET in TiO2 Unipolar RRAM (TsinghuU,Stanford U)
• 8.2 Modeling the Forming Stage of an RRAM by KMC Simulation (U. of Calif., Berkeley)
• 8.3 A Model for TMO RRAM Based on Electron Correlation Effects (U. of Colorado)
• 8.4 Stochastic Model of Switching in Bipolar MO RRAM (TU View, Volgograd Tu)
• 8.5 A Unified Model for The Reset Mechanism of Metal Oxide RRAM (Stanford U.)
• 8.6 Potential Models for Switching Characteristics of HfO2 based RRAM
• 8.7 Model for RRAM I-V Characteristics (Peking University)
• 8.8 Monte Carlo Simulation of Hysteresis in RRAM (Technical Univ. Of Vienna)
• 8.9 HRS Retention Model for MO RRAM(PekingU, StateUNY, NanyangTechU, A*STAR)
• 8.10 KMC Simulator for Studying Properties of ECM RRAM (U. Of Calif., Berkeley)
• 8.11 Modeling of Switching Mechanism in Oxide-Based Memory (Tech. U. Of Vienna)
• 8.12 Monte Carlo Simulation Method for RRAMs (U. Of Calif., Berkeley)
• 8.13 Defect Model for a MIM based ReRAM (IM2NP-UMR, U. de Provence)
• 8.14 Numerical Modeling of RESET Programming in a NiO RRAM (Politech. di Milano)
• 8.15 Oxygen Ion Transport Model for Metal Oxide RRAMs(Peking U., State U. of N.Y.)

9.0 Reliability of ReRAM Devices

• 9.1 Unipolar NiO RRAM Ireset & SET-RESET Instability (Polit.diMilano, IMM-CNR)
• 9.2 Effect of Crystallinity of HfO2 on RRAM Switching Reliability (Hynix)
• 9.3 Variability of RRAMs and Crossbar Array Performance (Global Foundries)
• 9.4 Random Telegraph Noise in Amorphous TIOx RRAM (Seoul Nat. Univ.)
• 9.5 Model Linking TDDB with CF Forming in HfO2 (U.di MeRE, Sematech,IUNET)
• 9.6 RESET Instability in a Cu/ZrO2:Cu/Pt RRAM (Chin. Acad. of Sci. , Lanzhou U.)
• 9.7 Retention Failure in Bipolar MO RRAM (PekingU,NanyangTechU,U Albany, A*STAR)
• 9.8 Radiation Resistant HfO2-Based RRAMs (Lanzhou U., Chin. Acad. of Sci., SUNY)
• 9.9 Data Retention & RESET Current Trade-Off in NiO RRAMs (Politech. di Milano)
• 9.10 Study of Current Compliance Failure Phenomenon in ReRAM (Peking University)
• 9.11 Effect of High Temperature Bias on an ReRAM Device(NanyangTI, A*STAR, PekingU)

10.0 Operation, Characterization and Test of RRAM Arrays

• 10.1 RRAM Stack Effect on Forming Voltage and Current Overshoot(SEMATECH, SUNY)
• 10.2 Improved Uniformity in RRAM with Current Driving (Chinese Academy of Science)
• 10.3 Characterization of HfOx/AlOx Bi-Layer RRAMs (Stanford U.)
• 10.4. Fab Friendly Materials for Low Power RRAM (SEMATECH, Canon ANELVA)
• 10.5 Using TDDB to Analyze RRAM Switching Using CF (IMEC, K.U. Leuven)
• 10.6 Operation of an RRAM Array Built in CMOS Metallization (Unity Semiconductor)
• 10.7 Characterization of a 1-Kb array of 1T1R HfOx RRAM (various Taiwan Universities)

11.0 Selection Devices in Metal Oxide ReRAMS

• 11.1 Heterostructure Diodes forSneak Current in ZnO RRAM Crossbar Array(KAIST)
• 11.2 TiO2 MIM Selection Device for TiO2 RRAM Cross-Point Array (Gwangju IST)
• 11.3 4F2 CMOS Cross-Bar HfO2 ReRAM with Vertical BJT Access(NTHU, ITRI)
• 11.4 TiOx Diode Selection Device in a 1D1R ReRAM Cell (Nat. Chiao-Tung Univ.)

12.0 3-D Cross-Point RRAM Arrays

• 12.1 Ni/HfOx/n+ Si Unipolar RRAM Cross-Bar+ Si Diode (Nanyang,NUS Soitec,Fudan)
• 12.2 Peripheral Design for Cross Point Memristor-based RRAM (Penn. State Univ.)
• 12.3 3D Bipolar ReRAM Forming Memory Islands (NYU)
• 12.4 Crossbar ZrO2 RRAM built on a foundry platform substrate (Chin. Acad. Of Sci)
• 12.5 RESET-SET Instability in ReRAM Cross-Bar Array(Politechnico di Milano)
• 12.6 10 uA Ireset in Diode Crossbar RRAM (Polit. Di Milano, IUNET, IMM, CNR, IMEC)
• 12.7 Memristor-Based Hybrid Reconfigurable Logic (Hewlett Packard Labs)
• 12.8 Stacked 3-D NiO RRAM with CuO diode and GIZO peripheral TFT (Samsung)

13.0 Programmable Logic Using RRAM

• 13.1 CMOS FPGA and Routing Switches Made with RRAM Devices
• 13.2 Solid Electrolyte Switch Embedded in A Copper Interconnect (NEC)
• 13.3 Memristor-Based Hybrid Reconfigurable Logic (Hewlett Packard Labs)

14.0 Developers and Vendors of Resistance RAMs

• 14.1 Adesto Technologies
• 14.2 Global Foundries
• 14.3 Hewlett Packard
• 14.4 Hynix
• 14.5 IBM
• 14.6 IMEC
• 14.7 Macronix
• 14.8 Nanya
• 14.9 NEC
• 14.10 Samsung
• 14.11 Sharp
• 14.12 Sony
• 14.13 ST Microelectronics
• 14.14 TSMC
• 14.15 Unity Semiconductor
• 14.16 Winbond
• 14.17. 4DS

Bibliography

Overview | Contents

To order "Resistance RAM Technology & Development, July 2011": 

Contact Memory Strategies or
Send us the information requested below by e-mail, fax, or post along with your check, bank transfer, or purchase order for $975. ($850 if a Technical Market Analysis has been ordered from Memory Strategies in the past year.)

ORDER FORM: Please send ______ copies of  "Resistance RAM Technology & Development, July 2011" to:

Report Format

____ PDF. Will be sent by email. Please send your order by email, if possible. Printing hardcopy from PDF is permitted.

____ (Hardcopy of report only available for shipping within USA. We apologize for any inconvenience.
           Report will be sent by 2-Day FedEx. Please send all information requested above.)
         If you wish both PDF and Hardcopy, please add an additional USD200 to your order

Submit Order and Payment Information via:
    Email: info@memorystrategies.com, or
    Fax:    +1 512 900 2846
    Post:
        Memory Strategies International,
        16900 Stockton Drive,
        Leander, Texas 78641, U.S.A.

To pay by:

• Credit Card: please fax credit card information to +1 512 900 2846
• Bank Transfer: please send in your order and request transfer details.
• Purchase Order: submit purchase order details with order.

For more information, please Contact Memory Strategies