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A Memory Strategies Focus Report

Resistance RAMs , May 2010

(ReRAM, RRAM, Metal Oxide RAM, Memristor, PMC-RAM, CB-RAM)

This report covers resistance RAMs in various technologies along with cell and element structures, and cross-bar arrays made of these cells. These small cell, high density non-volatile memory devices are thought to be possible successors of the current non-volatile memory devices in the < 20 nm technologies. The memristor is discussed since resistance RAMs operate like a classical memristor.  Complex and binary metal oxide elements in RRAMs are discussed using many different materials. Memories of these materials are covered separately including cells, arrays and characterizations that have been performed. Cross-bar arrays using RRAM elements and various selection devices are discussed. The programmable metallization cell, which uses metal conducting filaments in an electrolyte, is included and several discussions covered. Various new materials which have been shown to exhibit resistance switching are included. The recent work of companies that are potential vendors of these various memory technologies are then summarized.

70+ pages.

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Table of Contents - Resistance RAMs, May 2010

1.0 Overview of Resistance RAMs

2.0 Applications For Resistance RAMs

• 2.1 Storage Class Applications for Resistance RAMS
  • 2.1.1 Overview of Storage Class Memory
  • 2.1.2 Enterprise Storage Applications for ReRAM
• 2.2 SSD Applications for ReRAM
• 2.3 embedded memory and logic applications

3.0 Cell Sizes vs. Technology for Resistance RAMs

4.0 Metal Oxide Memory Elements

• 4.1 Overview of Metal Oxide Memory Elements
• 4.2 Basics Metal Oxide Unipolar and BiPolar Switching Due to Conductive Filaments
  • 4.2.1 Basics of Unipolar Switching
  • 4.2.2 Basics of BiPolar Switching

5.0 Technical Issues and Mechanisms of Various Material RRAMs

• 5.1 Technical issues and Mechanisms of Zirconium (Zr) Metal Oxide Memories.
  • 5.1.1 Electrical Properties and Structures of ZrTiO4 Thin Film for ReRAM (Nat. United .U.)
  • 5.1.2 Resistance Variations During Switching of a SrZrO3 RRAM (Nat. Chiao Tung U.)
  • 5.1.3 Resistance Switching of Cu doped ZrO2 (Chinese Academy of Science)
  • 5.1.4 SrZrO3:Cr Metal-Oxide-Metal Structures (Korea Inst. of Sci. and Tech.)
• 5.2 Technical Issues and Mechanisms of Niobium (Ni) Metal Oxide Memories
  • 5.2.1 Vertical Cross-Point NiO Transition Metal Oxide RRAM (Samsung)
  • 5.2.2 Confined TMO NiO RRAM Cell for Improved Uniformity ( Stanford Univ.)
  • 5.2.3 Characterization of NiO RRAM in Low Resistance State (Politechnico di Milano)
  • 5.2.4 Model for Physical Switching Mechanism in NiO Memory (Politechnico di Milano)
  • 5.2.5 Integration of NiO Memory Structures in Interconnect Structures (U. of Sud Toulon)
  • 5.2.6 ReRAM Made with NiO Doped with Ti:NiO (Fujitsu)
• 5.3 Technical Issues and Mechanisms of Titanium (Ti) Metal Oxide Memories
  • 5.3.1 90 nm TiN/TiON RRAM Cell in CMOS Logic Technology (Nat. Tsing-Hua U,TSMC)
  • 5.3.2 ReRAM Stacks Using Ta2O5 and Thin TiO2 (NEC)
  • 5.3.2.1 RTN and Retention of Bottom Electrode of Ta2O5/TiO2 ReRAM Stack (NEC)
  • 5.3.2.2 Controlling Resistance in Multilevel and Low Voltage Ti2O5/TiO2 ReRAM (NEC)
  • 5.3.2.3 Effect of ReRAM Ta2O5/TiO2 Stack Asymmetry on Read Disturb Immunity (NEC)
  • 5.3.3 Memristor Pt/TiO2-x/Ti Cross-Bar Memory Devices
  • 5.3.3.1 Read and Write Model of Cross-Bar Pt/TiO2-x/Ti Memristor Memory (HP Labs)
  • 5.3.3.2 TiO2 Cross-Bar RRAM Functioning as a Memrestor (Hewlett Packard)
  • 5.3.3 Studies of TiO2 cross-bar array RRAMs (Forschungszentrum Julich)
  • 5.3.4 Resistance Switching of TiO Crossbar and Via Hole Devices (KAIST & ETRI)
• 5.4 Technical Issues and Mechanisms of HfO2 Metal Oxide Memories
  • 5.4.1 Uniformity Improvement Using Al-doped HfO2 ReRAM Materials(PekingU. andSUNY)
  • 5.4.2 1Kb HfO2 RRAM in 180 nm CMOS (ITRI, MingShin U., Tsing Hua U.)
• 5.5 Technical Issues and Mechanisms of CeOx Metal Oxide Memories
  • 5.5.1 Resistance Switching of CeOx Films (Peking Univ.)
• 5.6 Technical Issues and Mechanisms of Copper (Cu) Metal Oxide Memories
  • 5.6.1 Copper Doped MoOx / GdOx Bilayer Films (Gwangju Inst. of Sci. & Tech.)
  • 5.6.2 Bistable Resistance Switching in CuO Thin Films (Pusan Nat. Univ.)
  • 5.6.3 CuxO RRAM Made by Growing CuO in Plasma Oxidation (Fudan U.)
  • 5.6.4 Resistance Switching in Cu2O by Charge Tapping Conductivity Modulation (Spansion)
  • 5.6.5 CuO RRAM Cells (Fudan University)
• 5.7 Technical Issues and Mechanisms of Tungsten (W) Metal Oxide Memories
  • 5.7.1 Unipolar WOx Memory (Nat. Chiao Tung U.)
• 5.8 Technical Issues and Mechanisms of Aluminum Metal Oxide Memories
  • 5.8.1 Unified Memory Resistance RAM Using Al2O3 Film

6.0 Characterization and Modeling of Metal oxide Memory Cells

• 6.1 Defect Model for a MIM based RERAM ((IM2NP-UMR, U. de Provence)
• 6.2 Numerical Modeling of RESET Programming in a NiO RRAM (Politech. di Milano)
• 6.3 Oxygen Ion Transport Model for Metal Oxide RRAMs(Peking U., State U. of N.Y.)
• 6.4 Characterization and Modeling of Metal Oxide RRAMS (Peking University)
• 6.5 Characterization of Switching Mechanisms in Metal Oxides(Gwangju Inst.)
• 6.6 Modeling a Percolation Process for a TiO2 and a HfO2 RRAM (Peking Univ.)
• 6.7 Physical Model of ZnO Cell (Peking University)

7.0 Metal Sulfide RRAM Memories

• 7.1 Overview of Metal Sulfide RRAM
• 7.2 Copper Sulfide Memories
  • 7.2.1 Cu2S Memory Cells Made using Pulsed Laser Deposition (Jiangsu Univ.)

8.0 Selection Elements in Metal Oxide ReRAMS

• 8.1 TiOx Diode Selection Device in a 1D1R ReRAM Cell (Nat. Chiao-Tung Univ.)

9.0 3-D Stacking of Cross-Point RRAM Devices

• 9.1 Memristor-Based Hybrid Reconfigurable Logic (Hewlett Packard Labs)
• 9.2 Stacked 3-D NiO RRAM with CuO diode and GIZO peripheral TFT (Samsung)
• 9.2 Studies of TiO2 cross-bar array RRAMs (Forschungszentrum Julich)

10.0 Characterization and Test of RRAM Arrays

• 10.1 Characterization of a 1-Kb array of 1T1R HfOx RRAM (various Taiwan Universities)

11.0 Programmable Logic Using RRAM

• 11.1 Solid Electrolyte Switch Embedded in A Copper Interconnect (NEC)
• 11.2 Using RRAM to Build 3-D FPGA (Chinese Academy of Science)

12.0 Conductive Bridge/Programmable Metallization Cell Memories

• 12.1 Background of Conductive Bridge RAMs
• 12.2 Technical Issues of Programmable Metallization Cell Resistance Switches
  • 12.2.1 PMC Memory for Storage Class Applications (Adesto Technologies)
  • 12.2.2 Study of CB-RAM Resistance Ratio vs. Electrode Size (Samsung, Sejong U.)
  • 12.2.3 Kinetic Study of PMC / CB-RAM (Politechnico di Milano, U. of Arizona)
• 12.3 Kinetics of Programming ML Cells in PMC Memory (Politechnico di Milano, ASU)

13.0 Other Resistance Switching Materials

• 13.1 Low Resistance State Stability for a Pt/Cu:MoOx/GdOx/Pt ReRAM Device (Gwangju)
• 13.2 FeO and ZnFe Superlattices for ReRAM (Missouri Univ. of Sci. and Tech.)
• 13.3 Resistance Switching of Carbon-Based Resistance Memory Cells ((Tshinghua Univ.)
• 13.4 Resistance Switching of Perovskite Oxide based Memory Device (Gwangju, Hynix)
• 13.5 BiStable Resistance Switching Using LSMO (Tsinghua University)
• 13.6 Resistance Switching Behavior of Si3N4 (Peking University)

14.0 Developers and Vendors of Resistance RAMs

• 14.1 Adesto Technologies
• 14.2 Hewlett Packard
• 14.3 Hynix
• 14.4 IBM
• 14.5 IMEC
• 14.6 NEC
• 14.7 Samsung
• 14.8 Spansion
• 14.9 Unity Semiconductor
• 14.10 4DS

Bibliography

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