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Standalone Flash Memory Technology
( Floating Gate, Charge Trap, MLC, Multi-bit, 3-D, Stacked, Nanowire)
February 2011

The report discusses the technology, development and applications of high density standalone flash memory. It includes both floating gate and charge trapping flash and both NAND and NOR architectures. Applications include HDD, SSD, Multi-Media, Digital Portable Systems, USB drives, games consoles, Notebook PC's and UMPC, Cache Buffers, Set-Top boxes and memory cards. Floating Gate technology issues include tunnel oxide engineering, interlayer dielectric barrier engineering and channel engineering. Charge trapping issues include: bandgap engineered cells such as BE-SONOS, FinFET, nanowire memory, TFT and surrounding gate devices. Charge trapping devices using high-k dielectric and high work-function gates are explored including TANOS, MOHOS, MANOS, etc. 3-D and vertical pipe NAND flash cell structures are covered. Reliability, test and modeling issues for charge trapping memory and floating gate flash are covered. Vendors and developers of standalone flash and discussed. 160+ pages.

DESCRIPTION | TO ORDER

Standalone Flash Memory Technology
(Floating Gate, Charge Trap, MLC, Multi-bit, 3-D, Stacked, Nanowire)
February 2011

Table of Contents

Executive Overview:

1.0 Overview of Standalone Flash Memory

2.0 Flash Memory Applications

• 2.1 Overview of NAND Flash Applications
• 2.2 Solid State Drives (SSD)
• 2.2.1 SSD for PC Computers
• 2.2.2 SSD for Servers
• 2.2.3 SSD for RAID Applications
• 2.2.4 Flash for Moble Computing (Replacing Hard Disk Drives (HDD)
• 2.3 USB NAND Flash Drive
• 2.4 NAND in Consumer Mobile Devices
• 2.4.1 NAND in Digital Still Cameras:
• 2.4.2 Smart Phones
• 2.4.3 Netbook PCs
• 2.4.4 Multimedia Storage Using Flash Memory
• 2.5 Gaming
• 2.5.1 Gaming Consoles
• 2.5.2 Flash Cards for Game Machines
• 2.5.3 256-GB SSD for PC Gaming
• 2.6 Controllers for NAND Flash Memory Cards
• 2.6.1 JEDEC eMMCv4.3 NAND Card Controllers
• 2.7 NOR Flash Applications
• 2.7.1 Overview of NOR Flash Applications
• 2.7.2 Medical Applications
• 2.7.3 Automotive Systems
• 2.7.4 Multimedia and Feature Cell Phones
• 2.7.5 Industrial Applications
• 2.7.6 Consumer Applications

3.0 Flash Memory Cell Size by Technology Node

• 3.1 Various Flash Storage Cell Sizes for Different Technologies and Flash Types
• 3.2 Density Trend of NAND Flash Technology

4.0 Floating Gate Flash Cell Technology

• 4.1 Dual Layer FG Structure for Fully Planar sub-30 nm Flash (IMEC, ASM)
• 4.2 Effect of Depth of Recess of STI on Vth Distribution and Vth Shift (Powerchip)
• 4.3 Floating Gate Silicon Nitride Cap for 20 nm NAND Flash Memory (Samsung)
• 4.4 Bandgap Engineering of Tunnel Oxide of a NAND Flash (Samsung)
• 4.5 Evaluation of Barrier Engineering for Floating Gate flash memory
• 4.6 Performance Improvement with OAO IPD in Flash Memories (Samsung)
• 4.7 Improving Floating Gate Performance with thin LaSiO ILD (N. Carolina State U.)
• 4.8 Electron Trap Properties in IPD of Flash Cells(Liverpool John Moores U, IMEC)

5.0 Floating Gate NOR Flash Technology

• 5.1 Basic Limit to Width of Vt Dist. in NOR Flash (Polit.di Milano, Numonyx, CNR)
• 5.2 Shallow Trench Isolation Process for Floating Gate NOR Flash Memory
• 5.3 1-Gb 45 nm Floating Gate NOR Flash Using Self Aligned Contacts-SAC (Numonyx)
• 5.4 NOR Flash Decoder for ECC in MLC NOR flash memory

6.0 NAND Flash Floating Gate

• 6.1 NAND Flash Floating Gate Technology
• 6.1.1 32-Gb MLC 26 nm NAND Flash With Negative WL and Improved Vth (Hynix)
• 6.1.2 FG Poly Depletion Effect on Erase Efficiency of NAND (Numonyx, Polit.di Milano)
• 6.1.3 Optimal Cell Design for 32 nm Floating Gate NAND Flash (Samsung)
• 6.1.4 Word-Line to Word-Line Disturb During Program in FG NAND Flash Memory
• 6.1.5 Variability Effects on Vt Distribution in FG NAND Flash (Numonyx, Pol di Milano)
• 6.1.6 Dependence of Vt on Adjacent Cells in a NAND Flash Array (Politecnico di Milano)
• 6.1.7 Planar FG and CT NAND Device Using a trapping IPD for Storage (Macronix)
• 6.1.8 Floating Gate Planar sub-50 nm BE -SONOS NAND Flash Cell (Macronix)
• 6.2 Multiple Level Two Bits/Cell Floating Gate NAND Flash Technology
• 6.2.1 64 Gb 151 mm2 MLC NAND Flash in 24 nm CMOS (Toshiba, Sandisk)
• 6.2.2 A 25 nm 64-Gb MLC NAND Flash (Micron)
• 6.2.3 32-Gb MLC 32 nm NAND Flash with Vth Endurance Enhancing (Hynix)
• 6.2.4 32-Gb 34nm 2-bit MLC NAND with 50 us read/900 us program (Intel, Micron)
• 6.2.5 8-GB 2-bit/cell MLC 25 nm NAND Flash (Intel, Micron Tech.)
• 6.2.6 Floating Gate MLC NAND Flash in 30 nm Technology (Toshiba)
• 6.2.7 Incremental Step Pulse Programming of < 40 nm MLC NAND flash (Samsung)
• 6.3 3-bit/Cell Multilevel NAND Flash
• 6.3.1 A 27 nm Multi-Level 3bit/cell NAND FG Flash Memory (Samsung)
• 6.3.2 Production Ready 32 nm 3-bit MLC 32-Gb NAND Flash(Samsung)
• 6.3.3 3bit/cell 34 nm 32-Gb NAND Flash with 6 MB/s Throughput (Micron, Intel)
• 6.3.4 32-Gb 3-bit/cell MLC 30 nm NAND Flash (Samsung)
• 6.3.5 32-Gb 8-Level 3-bit/cell 48 nm NAND Flash Memory (Hynix)
• 6.3.6 8-MB/s 3-bit MLC 56 nm NAND Flash (SanDisk and Toshiba)
• 6.4 4-bit Multilevel NAND Flash
• 6.4.1 64Gb 4b/cell 43 nm NAND Flash with 5.6 MB/s Programming (SanDisk&Toshiba)

7.0 High Throughput DDR NAND Flash

• 7.1 7 MB/s 64Gb 20 nm DDR NAND Flash with 3-bit/cell Storage (Samsung)
• 7.2 32 Gb 32 nm NAND Flash with 200 MB/s Asynchronous DDR Interface (Samsung)
• 7.3 32-Gb NAND Flash with 6 MB/s DDR Throughput (Micron, Intel)

8.0 3-D Vertical Stacking of NAND Flash Transistors

• 8.1 3-D Stacking of NAND Flash in Charge Trapping Technology
• 8.1.1 3-D Stacked NAND Flash with Single Crystal Si Channel Body Stacks (Seoul Nat. U.)
• 8.1.2 3-D Vertical Cylindrical Floating Gate Cell Structure (Tohoku University)
• 8.1.3 3D TCAD Simulations of Vertical NAND Flash Architectures (Macronix)
• 8.1.4 3-D Stacked NAND Flash String Using Common Gate and Shield(Seoul Nat. U.)
• 8.2 3D High Stacked Charge Trapping TFT NAND Flash Memory (Macronix)
• 8.2.1 Vertical Gate TFT NAND Flash Buried Channel BE-SONOS Array (Macronix)
• 8.3 Bit Cost Scalable (BiCS) Charge Trapping Pipe NAND Flash Technology (Toshiba)
• 8.3.1 Improved Piped BiCS NAND Flash Technology (Toshiba)
• 8.3.2 Bit-Cost Scalable Floating Pillar Vertical SONOS NAND Flash Memory (Toshiba)
• 8.3.3 Multi-level 32-Gb Pipe-Shaped BiCS NAND Flash Memory (Toshiba)
• 8.4 Vertical SONOS Charge Trapping Pipe NAND Flash (Samsung)
• 8.4.1 Damascene W Metal Gate SONOS Vertical NAND Flash String"TCAT"(Samsung)
• 8.4.2 Vertical NAND Chains "VSAT" with "PIPE" Process (Samsung)
• 8.4.3 Vertical Gate NAND Flash with Eight Active Layers (Samsung)
• 8.5 3-D Pipe Floating Gate NAND Flash Cell
• 8.5.1 3-D PipeFloating Gate NAND Flash Cell (Hynix)

9.0 Stacked NAND Flash Systems and Inductive Signaling Between Chips

• 9.1 Stacked NAND Flash Using Inductive Coupling
• 9.1.1 Inductive Coupling to Replace TSV in Low Power CMOS Integration (Keio Univ.)
• 9.1.2 New Channel Coil Method for Inductive-Coupling of NAND Flash Stacks (Keio U.)
• 9.1.3 2Gb Inductive Coupling for 128 Die NAND Flash Stacking (Keio University)
• 9.1.4 Inductive Coupling Programmable Bus for NAND Flash in SSD(Keio U.,U.of Tokyo)
• 9.1.5 Wireless SSD Communication To Controller & 64 NAND Flash (Keio U, U.Tokyo)
• 9.1.6 High Density NAND Flash Stack with Controller (Toshiba)
• 9.2 Through Silicon Vias for Stacking Flash Memory 9.2.1 Through Silicon Via Interconnects Under the Bond Pads on NAND Flash (ASTRI)

10.0 Charge Trapping Flash Technology

• 10.1 Bandgap Engineered (BE) Node Folded NAND Flash (Seoul Nat. U., Stanford U.)
• 10.2 MONOS Flash With 3.6 nm ENT Trapping Layer (NCTU, NTHU, Nanyang)
• 10.3 Engineered Potential Well for CT NAND Flash (KAIST, KIST, SungKyunkwan U.)
• 10.4 CT Flash with SiGe Buried Channel & New Charge Trap Layers(Nat. Tsing HuaU)
• 10.5 2-Bit/Cell & MLC SONOS with Wrapped SG in NOR Flash(SSS, UMC,SCTU,FCU)
• 10.6 Modeling of Barrier Engineered Charge Trapping NAND Flash
• 10.7 Vertical Channel BE-SONOS NAND Flash (Seoul National Univ.)
• 10.8 Origin of Erase Improvement in Si-Rich MONOS Memories (Toshiba)
• 10.9 Using RTS to Determine Lateral Spread of Injected Charge in NOR SONOS Flash
• 10.10 High Temperature Anneal of Al2O3 Blocking Layer in CT Memory (Kaist)
• 10.11 MOHOS Memory with High-K Trapping Layer of Yb2TiO5 (Chang Gung U.)
• 10.12 Vertical Channel Multibit 3-D SONOS NOR Flash Architecture (Seoul Nat. U.)
• 10.13 Lateral Charge Distribution in 40 nm Split-Gate SONOS (NEC)
• 10.14 Hot Electron Program in Low Vds SONOS with Buried Diffusion BL (Macronix)
• 10.15 Arch NAND Flash Memory array (Seoul Nat. Univ.)
• 10.16 Bottle Shaped Gate Profile to Reduce Stringers om 45 nm CT Flash (Macronix)
• 10.17 Effect of S/D Dopant Concentration in Charge Trap NAND Flash (Macronix)
• 10.18 Single and Bandgap Engineered ONO Tunnel Dielectric (Seoul Nat. U.)
• 10.19 Endurance of BE-SONOS NAND with Nitrided Tunnel Ox/Si Interface (Macronix)
• 10.20 Overview of Sub-30 nm Barrier Engineered NAND Flash CT (Macronix)
• 10.21 Independent Double Gate Fin SONOS Flash Memory (Samsung, Seoul Nat. U.)
• 10.22 20 nm MONOS Technology for NAND Flash (Toshiba)
• 10.23 High-K BE Trapping Layer for MLC Flash (Chinese Acad. of Sci.)
• 10.24 Study of EOT of the Bandgap Engineered Tunnel Layer in SONOS (Seoul Nat. U.)
• 10.25 SONOS Using Dynamic Threshold Program (UMC, SSS, NCTU,FCU)

11.0 SONOS Nanowire Memory

• 11.1 Making Side-Gate, Omega-Gate and Gate-All-Around NW Memory (NCTU, NNDL)
• 11.2 Nanowire FET with Double-Gated SONOS Type Flash (Nat. Chiao Tung U., NNDL)
• 11.3 Interface Traps in Silicon Nanowire MOSFET
• 11.4 Overview of 3D Nanowire Technology
• 11.5 Multibit ProgramVertical Channel Si NW Flash Memory(Nanyang Tech U, A*STAR)
• 11.6 Vth Shift Characteristics of Gate- All-Around SONOS/TANOS NV(Seoul Nat. Univ.)
• 11.7 Cone-Type SONOS Cell for Improved Performance Characteristics (Seoul Nat. Univ.)
• 11.8 Improved Erase in Nanowire SONOS by Using a Silicide Drain (Seoul Nat. U.)
• 11.9 Gate-All-Around SONOS with Double Gate Memory(CEA-LETI, MINATEC, IMEP)
• 11.10 Low Temp Poly-Silicon Field Enhanced Nanowire SONOS (Nat. Chiao Tung U.)
• 11.11 Model of Cylindrical GAA Charge Trap Memory(U.of Bologna, ASTAR)
• 11.12 3-D Flash Using Gate-All-Around SONOS with Vertical Si Nanowire (A- Star)
• 11.13 Tri-Gate Polysilicon Nanowire SONOS for Flat Panel Applications
• 11.14 Gate-All Around Nanowire Twin SONOS Device(Inst.uElec., Nat. U.- Singapore)

12.0 Dopant Segregated Schottky Barrier (DSSB) Technology for NOR Flash

• 12.1 Schottky Barrier Multi-Bit Cell Using SSI Program and Hole Erase (NCNU, NTHU)
• 12.2 DSSB SONOS Flash for tight Vt control and MLC Operation (KAIST, ETRI)
• 12.3 Narrower Fin Width Using DSSB Technology for NOR Flash (KAIST)
• 12.4 Dopant Segregated Schottky Barrier SONOS NOR Flash (KAIST, EECS, ETRI)

13.0 New Charge Trapping Material and Unusual Stack Structures

• 13.1 Ferroelectric NAND Flash with Write Buffer (U.ofTokyo,NIAIST)
• 13.3 Multilayer Charge Trap Memories Using LaAlO3 (Yonsei University)
• 13.4 Engineered ONO & NON Tunnel Barriers in Charge Trapping Flash (Kwangwoon U.)
• 13.5 Potential Well Engineering for NAND Flash (SKKU, Korea Inst. of Sci.&Tech.)

14.0 MATHS/TANOS/MANOS-Type Al2O3 Dielectric Nitride Storage Flash

• 14.1 Hydrogen Origin of Traps in Al2O3 in TANOS NAND Flash (CEA-LETI MINATEC)
• 14.2 Scaling TaN FG with High-K Blocking Dielectric for Flash (N. Carolina State U.
• 14.3 MANAS CT Flash using MAD(Yale, Nat. Taiwan U.,Nanjing U.,Israel Inst.ofTech.)
• 14.4 Charge Trapping Flash Using a ZrON Trapping Layer (Nat. Chiao-Tung University)
• 14.5 N2 Implant in SOHOS Flash Device (Chung-nam Univ.)
• 14.6 Finding Electron Trap Energy in High-k Materials (Xidian U., Liverpool JMU, IMC)
• 14.7 GdAlO and LuAlO Blocking Dielectric for TANOS Flash Memories (IMEC)
• 14.8 La, Gd, Lu Aluminates for Use as Trap Materials in CT Flash (IMEC)
• 14.9 Effect of Nitridation of the HfON Layer of TANOS Memories (Univ. of Texas)
• 14.10 Charge Storage of HfON embedded in MAHnOS (Nat. Tsing Hua Univ.)
• 14.11 P/E Cycling Endurance in SANOS Memories (IIT Bombay, Applied Materials)
• 14.12 TANOS Cells with Sealing Oxide between Si3N4 and Al2O3 (Infineon, PTB, NML)
• 14.13 MOHOS Flash Memory Using Tb2O3 Trapping Layer (Chang Gung U.)
• 14.14 Data Retention Study of 40 nm TANOS Charge Trap Flash (Samsung)
• 14.15 Effect of Hydrogen Annealing on MANOS Reliability (Korea U.,Seoul)
• 14.16 Alumina Trapping & Leakage Effects on TANOS Reliability(Politecnico di Milano)
• 14.17 Post Gate Etch Plasma ReOx on TANOS Flash Memory (SEMATECH)
• 14.18 Select Transistor Swing Degradation in TANOS Flash Memories (Samsung)
• 14.19 Holes & Electrons During Erase of TANOS Memories (U. di MeR Emilia, IMEC)
• 14.20 Comparison of HfO2 and Si3N4 Charge Trap Layers (Kwangwoon U.)
• 14.21 Properties of Al2O3 Stacks for Flash Memory (U. Autonoma de Barcelona)
• 14.22 Charge Loss Behavior of "ONA" Charge Trapping Flash (Gwangju)
• 14.23 Electrical Characteristics of High Work-Function Metal Gate TANOS Flash (IMEC)
• 14.24 Engineering a MANOS Flash for Improved Retention(Sematech, Stanford, TSU)
• 14.25 Measuring the Trapping Efficiency of a TANOS NAND Flash (IMEC)
• 14.26 SONOS with HfO2 for the Capping Layer in SONOS Memory (U. of Erlangen)

15.0 3D and FINFET Charge Trapping Flash Memory

• 15.1 Triple Level Cell Characteristics in Sub-20 nm NAND Technology (Hynix)
• 15.2 RTN Effects in planar and FinFET SONOS Cells (Macronix & Nat. Chiao- Tung U)
• 15.3 Fast Dopant Segregated Schottky Barrier FinFET NAND SONOS at < 30 nm (KAIST)

16.0 TFT Charge Trapping Storage

• 16.1 Thin Film IGZO Flash Memory (National Cheng Kung U.)
• 16.2 TFT EEPROM Using Twin Poly and Nitride Trapping Layer(Nat. Tsing HuaU.)
• 16.3 Sub 30 nm TFT Charge Trapping NAND Flash (Macronix)
• 16.4 Tri-Gate Polysilicon Nanowire TFT SONOS for Flat Panel Applications
• 16.5 50 nm Vertical Double Gate 64 Cell 3D TFT SONOS (Schiltron)

17.0 Floating Gate Flash Simulation, Test, Modeling and Reliability

• 17.1 Program Disturb&Channel Leakage Current for Sub-20nm FG NAND (Micron, Intel)
• 17.2 Vth Fluctuation from RTN in FG NAND Flash (Hynix, Seoul Nat. Univ.)
• 17.3 32-Gb MLC NAND FG Flash Memory with Enhanced Vth Endurance (Hynix)
• 17.4 Heavy Ion Effects on FG Flash (Univ. di Padova)
• 17.5 Reliability of RTA Formed Gate SiON for FG Flash (Applied Mat., IIT- Bombay)
• 17.6 Retention Variability Sources in NAND FL Flash (Politec.di Milano, Numonyx, CNR)
• 17.7 CG&FG Design Effect on Electron Injection Spread (Politec. di Milano, Numonyx)
• 17.8 Flash Memory Modeled as a Percent of Ge in the Si Substrate (U. of Alabama)
• 17.9 MLC NAND Dyn. Vpass ISPP & Low Program Disturb (Samsung,SungkyunkwanU)
• 17.10 New ECC Code for Single and Multibit Errors in NAND Flash (Waseda Univ.)
• 17.11 Model for Parallel Programming of Flash Memories (U. of California)
• 17.12 Hot Electron BL Disturb During Programming of NAND Flash (U. of Braunschweig)
• 17.13 Vth Variation from RTN in NAND Flash Strings (Hynix, Various Univ.)
• 17.14 Total Ionizing Dose Response for Gb SLC NAND Flash (Jet Prop. Lab. of Caltech)
• 17.15 Sources of Drain Disturb in Nanoscale Flash (Peking University)
• 17.16 Hot Carrier Injection Reliability Degradation Characteristics (Hynix)
• 17.17 Cycling Induced Vth Instability for NAND Flash (Politecnico di Milano)
• 17.18 Neutron Effects on FG MLC NAND Flash(Various Italian U. & Companies)
• 17.19 Retention Reliability of 51 nm 16 -Gb NAND using SiO2/AlxOy/SiO2 IPD (Samsung)
• 17.20 Multibit Error Correction for < 32 nm NOR Flash (U. of Texas, Silicon Image)
• 17.21 Analytical Power Model of NAND SLC Flash Memory (U. of Virginia)
• 17.22 Random Dopant Effect Through Quick Electron Detrapping and RTS (Micron)
• 17.23 NAND Flash Heavy Ion Event Measurements
• 17.24 Improved Wear Leveling in Flash Memory (Nat. Taiwan Univ.)
• 17.25 Spread Programming to Reduce Bit Errors in NAND Flash (Samsung)
• 17.26 Ballistic Current in Scaled FG NAND Flash (Stanford, and Intel)
• 17.27 New Program/Erase Degradation Mechnism for FG NAND at 51-31nm (Samsung)
• 17.28 Formula for Predicting RTN Instabilities Flash(Numonyx, Polit.diMilano)
• 17.29 Low Freq Noise Characteristics of 70 nm NAND(Hynix, Kyungpool U,Daegu U)
• 17.30 Analysis of TID Effects on NAND Flash Circuits (Univ. of Padova)
• 17.31 Multilevel Cell NAND Flash System Durability Improvement (Hanyang U.)

18. Reliability and Test Issues for Charge Trapping Storage Memory

• 18.1 Degradation From Oxygen Defects in SiN Charge Trap MONOS (U.Tsukuba,OsakaU)
• 18.2 Reliability of 75nm & 38 nm Half- Pitch BE-SONOS CT NAND Flash (Macronix)
• 18.3 Fast Initial Charge Loss in Charge Trapping NAND Flash (Macronix)
• 18.4 Study of Charge Loss Mechanisms in Planar and STI Charge Trap Flash (Samsung)
• 18.5 Charge Gain/Vt shift in Nitride Charge Trapping Devices (Saifun/Spansion)
• 18.6 Reliability Issues in SONOS Flash Due to Tapered Nitride Profile (Macronix)
• 18.7 Bandgap Tunable SiON Tunnel Barrier for BE-SONOS NAND Flash (Macronix)
• 18.8 Electron/Hole Injection Statistics of BE-SONOS NAND Flash (Macronix)
• 18.9 ScOx Thin Layers for High-K material for Flash (U. Completense de Madrid)
• 18.10 Effect of Tunnel Oxide Nitridations on Flash Reliability (Applied Mat. , IMEC)
• 18.11 Effect of Edge Fringing Field Effect of STI on CT NAND Flash (Macronix)
• 18.12 Reliability Improvement in 20 nm MLC NAND Flash Planar MONOS Cell (Toshiba)
• 18.13 Resolving Fast Vth Transients After P/E of Flash Memory Stacks (IMEC&ESAT)
• 18.14 Charge Trapping Mechanisms of MONOS with High Endurance (U. of Tsukuba)
• 18.15 Radiation Hardened Read Circuit for SONOS EEPROM (TsingHua Univ.)
• 18.16 Endurance Issues in SONOS Due to Degradation of Top&Bottom Oxides (Macronix)
• 18.17 Charge Granularity Effect During NOR Flash CHE Program(Politecnico di Milano)
• 18.18 Statistical Retention Study of ONO Gate Stack Scaling in 50nm FG Flash (Samsung)
• 18.19 Effect of SiN Deposition on Charge Trapping Retention and Performance (Numonyx)

19.0 Modeling and Simulation for Charge Trapping Memories

• 19.1 Statistical Effects in Nitride Flash Memories (Numonyx, Politecnico di Milano)
• 19.2 Model Describing Charge Trapping and Transport in MANOS(U.di Modena e Reggio)
• 19.3 Simulation of Electron Trap Energy in High-K for Flash (IMEC,John Moores U)
• 19.4 Charge Trap Mechanisms of Nitride -Based NV Memories(CEA, LETI, MINATEC)
• 19.5 Simulations for Warm Electron Injection in Double Gate SONOS (U. of Calabria)
• 19.6 Programming Mechanism Wrapped Select Gate NOR SONOS(UMC,SSS, CTU,FCU)

20.0 Peripheral Circuits Used with Scaled Flash memory

• 20.1 WL Voltage Generator to Compensate for Temperature Variation in Flash (Micron)
• 20.2 Fast 3D SSD with NAND Flash Channel Number Detector(U. of Tokyo, Toshiba)
• 20.3 Cross-Coupled Charge Pump for Low Voltage Flash Memory
• 20.4 Switchable Charge Pump Using Low Voltage Transistors (Kuwait University)

21. Vendors and Developers for

Standalone Flash Memory

• 21.1 Cypress
• 21.2 Hynix
• 21.3 IM Flash (Intel, Micron)
• 21.4 Macronix
• 21.5 Micron (Also See IM Flash Technologies)
• 21.6 Micron (Numonyx)
• 21.7 Sandisk
• 21.8 Samsung
• 21.9 Spansion
• 21.10 Toshiba and SanDisk (Flash Vision)
• 21.11 Toshiba

Bibliography:

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