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Standalone Flash Memory Technology, Product and Applications
( Floating Gate, Charge Trap/SONOS, 3-D, Stacked, Nanowire)
February 2010

This report discusses standalone charge storage flash memory technology along with recent products and applications for NOR and NAND flash devices. It covers recent floating gate and charge trapping NAND and NOR technology scaling announcements along with multilevel and multibit technologies and the various vertical charge storage technologies such as FinFET, vertical channel, gate-all-around, TFT, and nanowire. Advanced charged trapping flash using high workfunction gates and high-k dielectrics are included along with bandgap engineered devices. It also discusses fast DDR interface NAND flash, stacked charge storage technologies such as TSV and inductive coupling of large NAND stacks. The many reliability and simulation papers in this area are also discussed. 180+ pages.

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Standalone Flash Memory Technology, Product and Applications
( Floating Gate, Charge Trap/SONOS, 3-D, Stacked, Nanowire)
February 2010

Table of Contents

1.0 Executive Overview:

2.0 Overview of Standalone Flash Memory Market and Applications

• 2.1 Overview of Flash Memory Market
• 2.2 The NAND Flash Market and Applications
  • 2.2.1 Overview of NAND Flash Market
  • 2.2.2 Overview of NAND Flash Applications:
  • 2.2.3 HDD Applications
  • 2.2.3.1 Overview of HDD Applications
  • 2.2.3.3 A Journal-Based Block Image (JBI) Approach to Flash File Systems
  • 2.2.4 Disk Cache in Server Applications
  • 2.2.5 Multi-Media (Video, Games, GPS Maps) Cards
  • 2.2.6 Virtual Hard Disk Drives
  • 2.2.7 Solid State Drives (SSD)
  • 2.2.7.1 SSD for PC
  • 2.2.7.2 SSD for Notebook PC
  • 2.2.7.3 SSD for Servers
  • 2.2.7.4 SSD for Embedded Systems
  • 2.2.8 USB NAND Flash Drive
  • 2.2.9 Digital Still Cameras:
  • 2.2.10 Smart Phones
  • 2.2.11 Gaming
  • 2.2.11.1 Games Consoles
  • 2.2.11.2 Flash Cards for Game Machines
  • 2.2.11.3 256-GB SSD for PC Gaming
  • 2.2.12 Netbook PCs
  • 2.2.13 Cache Using NAND Flash for Embedded Systems
  • 2.2.14 Cache Buffer Replacement Policy for NAND in Mobile Devices
  • 2.2.15 Controllers for NAND Flash Memory Cards
  • 2.2.15.1 JEDEC eMMCv4.3 NAND Card Controllers
  • 2.2.15.2 Other Flash Card Controllers
  • 2.2.16 Set-Top Box and auBOX
  • 2.2.17 Flash Memory Cards
• 2.3 The NOR Flash Market and Applications
  • 2.3.1 NOR Flash Market Potential
  • 2.3.2 Overview of NOR Flash Applications
  • 2.3.3 Automotive Systems
  • 2.3.4 Multimedia and Feature Cell Phones
  • 2.3.5 Removable Flash SIM Memory Cards
  • 2.3.6 Industrial Applications
  • 2.3.7 Consumer Applications

3.0 Flash Memory Cell Size by Technology Node

• 3.1 Various Flash Storage Cell Sizes for Different Technologies and Flash Types

4.0 Floating Gate NOR Flash Product and Technology

• 4.1 1-Gb 45 nm Floating Gate NOR Flash Using Self Aligned Contacts-SAC(Numonyx)
• 4.2 50 nm Vertical Double Floating Gate Multi-bit NOR Flash Cell (Intel, Stanford)
• 4.3 Methodology for Scaling Split Gate NOR Flash to 65 nm (DSM Solutions)
• 4.4 50 nm Node Surrounding Gate Transistor NOR Flash (Tohoku U.)
• 4.5 NOR Flash Decoder for ECC in MLC NOR flash memory

5.0 Floating Gate and Multi-Level NAND Flash Product and Technology

• 5.0.1 Overview of NAND Flash Technology
• 5.1 Multi-Level NAND Flash in Sub 35 nm Technology
  • 5.1.1 32-Gb MLC 32 nm NAND Flash with Vth Endurance Enhancing (Hynix)
  • 5.1.2 32-Gb 34nm 2-bit MLC NAND with 50 us read/900 us program (Intel, Micron)
  • 5.1.3 8-GB 2-bit/cell MLC 25 nm NAND Flash (Intel, Micron Tech.)
  • 5.1.4 Floating Gate MLC NAND Flash in 30 nm Technology (Toshiba)
  • 5.1.5 32-Gb 3-bit/cell MLC NAND Flash (Samsung)
• 5.2 MLC NAND Flash in sub 45 nm Technology
  • 5.2.1 Incremental Step Pulse Programming of < 40 nm MLC NAND flash (Samsung)
  • 5.2.2 16-Gb 4-Level 2-bit MLC 43 nm NAND Flash (Toshiba and SanDisk)
  • 5.2.3 Multilevel Programmed 43 nm Floating Gate NAND Flash (Toshiba & Sandisk)
• 5.3 MLC NAND Fland in sub-60 nm Technology
  • 5.3.1 16-Gb 56nm 2-bit MLC NAND with 34 MB/s Programming (Toshiba&SanDisk)
• 5.4 3-bit Multilevel NAND Flash
  • 5.4.1 3bit/cell 34 nm 32-Gb NAND Flash with 6 MB/s DDR Throughput (Micron, Intel)
  • 5.4.2 32-Gb 8-Level 3-bit/cell NAND Flash Memory (Hynix)
  • 5.4.3 8-MB/s 3-bit MLC 56 nm NAND Flash (SanDisk and Toshiba)
• 5.5 4-bit Multilevel NAND Flash
  • 5.5.1 64Gb 4b/cell 43 nm NAND Flash with 5.6 MB/s Programming (SanDisk&Toshiba)
• 5.6 High Throughput DDR NAND Flash
  • 5.6.1 32 Gb 32 nm NAND Flash with 200 MB/s Asynchronous DDR Interface (Samsung)
  • 5.6.2 3bit/cell 34 nm 32-Gb NAND Flash with 6 MB/s DDR Throughput (Micron, Intel)
  • 5.6.3 8-Gb 50 nm NAND Flash with 200 MB/s DDR Interface (Intel, Micron)

6.0 3-D Stacking of NAND Flash Transistors

• 6.1 Overview of 3-D Stacking of NAND Flash Transistors
• 6.2 3D Bit-Cost Scalable SONOS NAND Flash Memory (Toshiba)
  • 6.2.1 Bit-Cost Scalable Floating Pillar Vertical SONOS NAND Flash Memory (Toshiba)
  • 6.2.2 Multi-level 32-Gb Pipe-Shaped BiCS NAND Flash Memory (Toshiba)
  • 6.2.3 Bit-Cost Scalable Floating Pillar ONON Flash Memory (Toshiba)
  • 6.2.4 Bit-Cost Scalable (BiCC) Flash Memory (Toshiba)
  • 6.2.5 3-D Structure to Increase NAND Flash Density (Toshiba)
• 6.3 Vertical SONOS NAND Flash (Samsung)
  • 6.3.1 Damascened Metal Gate SONOS Vertical NAND Flash String "TCAT" (Samsung)
  • 6.3.2 Vertical NAND Chains "VSAT" with "PIPE" Process (Samsung)
  • 6.3.3 Vertical Gate NAND Flash with Eight Active Layers
  • 6.3.4 3-D NAND Flash SONOS With Vertical Recess Array Transistor (Samsung, UCLA)
  • 6.3.5 3-D Stacked 45 nm Floating Gate 4-Gb NAND Flash Memory (Samsung)
• 6.4 Stacked NAND Flash Chip Systems and Inductive Signaling Between Chips
  • 6.4.1 2Gb Inductive Coupling for 128 Die NAND Flash Stacking (Keio University)
  • 6.4.2 High Density NAND Flash Stack with Controller (Toshiba)
  • 6.4.3 Wireless SSD Communication To Controller & 64 NAND Flash (Keio U, U.Tokyo)

7.0 Charge Trapping NOR Flash Technology

• 7.1 Lateral Charge Distribution in 40 nm Split-Gate SONOS (NEC)
• 7.2 Dopant Segregated Schottky Barrier SONOS NOR Flash (KAIST, EECS, ETRI)
• 7.3 Hot Electron Program in Low Vds NOR SONOS with Buried Diffusion BL (Macronix)
• 7.4 Punch-Through Immune Virtual Ground Trapping Storage Cell (Macronix). [145]
• 7.5 NROM NOR Using Back Bias HHI and Forward Bias Assisted CHEI (NCTU, CGU)

8.0 Charge Trapping NAND Flash Product and Technology

• 8.1 Overview of Sub-30 nm Barrier Engineered NAND Flash Charge Trapping (Macronix)
• 8.2 Independent Double Gate Fin SONOS Flash Memory (Samsung, Seoul Nat. U.)
• 8.3 20 nm MONOS Technology for NAND Flash (Toshiba)
• 8.4 NAND with Symmetric Inversion S/D Structure to Improve Disturb (Samsung)
• 8.5 A New Impact Ionization Program and BB Tunnel HH Erase for NAND (Macronix)
• 8.6 Bandgap Engineered Charge Trapping NAND Flash Technology
  • 8.6.1 Study of EOT of the Bandgap Engineered Tunnel Layer in SONOS(Seoul Nat. U.)
  • 8.6.2 Sub-40 nm Charge Trap NAND Using Band Engineered Tunnel Oxide (Samsung)
  • 8.6.3 BE-SONOS NAND Flash Replacing S/D Junctions with Gate Fringe Field(Macronix)
  • 8.6.4 BE-SONOS NAND Flash at Sub-20 nm Technology Node (Macronix)
  • 8.6.5 BE-SONOS With ONO above Charge Layer and Injection From Top Gate(Macronix)

9.0 Trapping Site Flash Storage With Four Bits Per Cell - Physical & Multilevel

• 9.1 Overview of Trapping Site Storage with Four Bits Per Cell
• 9.2 NROM Type Flash with Four-bit per Cell (Two Physical Bits and Two MLC)
  • 9.2.1 8-Gb NROM with 4-bit/cell (2 Physical Bits & 2 MLC) (Saifun, Netanya, SMIC)
  • 9.2.2 Mirror Bit NOR Quad Flash with Two Physical/ Two Multilevel (Spansion)
• 9.3 Trapping Site Storage with Four Bit/Cell Using High-k Trapping Layer
  • 9.3.1 4-Bit/Cell(2-P/2-ML)with Partially Crystallized HfO2 Trapping Layer(SKKU,NUS)
• 9.4 Four Physical Bit Per Cell Trapping Site Storage
  • 9.4.1 4b/Cell 8Gb NROM with Improved Write Speed (SMIC and Saifun/Spansion)

10.0 Gate-All Around SONOS Nanowire Memory

• 10.1 Overview of 3D Nanowire Technology
• 10.2 Cone-Type SONOS Cell for Improved Performance Characteristics (Seoul Nat. Univ.)
• 10.3 Improved Erase in Nanowire SONOS by Using a Silicide Drain (Seoul Nat. U.)
• 10.4 Gate-All-Around SONOS with Double Gate Memory(CEA-LETI, MINATEC, IMEP)
• 10.5 Low Temp Poly-Silicon Field Enhanced Nanowire SONOS (Nat. Chiao Tung U.)
• 10.6 Operational Model of Cylindrical GAA Charge Trap Memory(U.of Bologna, ASTAR)
• 10.7 3-D Flash Using Gate-All-Around SONOS with Vertical Si Nanowire (A-Star)
• 10.8 Tri-Gate Polysilicon Nanowire SONOS for Flat Panel Applications
• 10.9 Gate-All Around Nanowire Twin SONOS Device(Inst.uElec., Nat. U.- Singapore)
• 10.10 Gate-All-Around Nanowire SONOS NAND Flash String (Samsung)
• 10.11 Gate-All Around Twin Nanowire SONOS (Samsung)

11.0 High-k Dielectric and New Charge Trapping Material

• 11.1 SONOS Using High-k Dielectric Hafnium Materials as the Trapping Layer.
• 11.2 Potential Well Engineering for NAND Flash (SKKU, Korea Inst. of Sci.&Tech.)
• 11.3 Distribution of Traps in SOHOS and SONOS Flash Memory (Hitachi)
• 11.4 Charge Trap Memory with Combined Si3N4 and HfON Trapping Layers
• 11.5 SONOS with HfO2 Storage Layer & Dual SiO2/Si3N4 Tunnel Layer (SKKU&NUS)
• 11.6 SONOS with HfO2 for the Capping Layer in SONOS Memory (U. of Erlangen)

12.0 High Workfunction Metal Gate Charge Trapping Flash

• 12.1 Engineering a MANOS Flash for Improved Retention(Sematech, Stanford, TSU)
• 12.2 Mechanism and Erase Characteristics of MANOS Memories (Macronix)
• 12.3 Vertical paired sun-10 nm TANOS FinFET NAND Flash String (Samsung)
• 12.4 Measuring the Trapping Efficiency of a TANOS NAND Flash
• 12.5 Integration of 30 nm Multi-Level NAND Flash using 38 nm TANOS (Samsung)

13.0 3D and FINFET Trapping Site Storage

• 13.1 RTN Effects in planar and FinFET SONOS Cells (Macronix & Nat. Chiao-Tung U)
• 13.2 Fast Dopant Segregated Schottky Barrier FinFET NAND SONOS at < 30 nm (KAIST)
• 13.3 BE-SONOS FinFET NAND Flash Using Fin Tip Field Enhancement (Macronix)
• 13.4 Double-Gate & Tri-Gate FinFET SONOS Flash(STMicroelectronics, CEA-LETI, IMEC)

14.0 New Cell Structure Technology Development for Trapping Site Storage

• 14.1 Planar FG and CT NAND Device Using a trapping IPD for Storage (Macronix)
• 14.2 Floating Gate Planar sub-50 nm BE-SONOS NAND Flash Cell (Macronix)
• 14.3 MLC, Mb SG SONOS Using Dynamic Threshold Program (UMC, SSS, NCTU,FCU)
• 14.4 Dual Charge Storage Layers for Multi-Level Cell Storage (SKKU & NUS)
• 14.5 Quantum Confinement Effect for Hole Injection Efficiency in MONOS (Hitachi)
• 14.6 Unified Floating Body DRAM & NVM Using PD-SOI SONOS FinFET (KAIST)

15.0 TFT Nitride Trapping Site Storage

• 15.1 Sub 30 nm TFT Charge Trapping NAND Flash (Macronix)
• 15.2 Tri-Gate Polysilicon Nanowire SONOS for Flat Panel Applications
• 15.3 50 nm Vertical Double Gate 64 Cell 3D TFT SONOS (Schiltron)
• 15.4 TFT MONOS on Glass Substrate (ITRI and STAR)

16.0 Floating Gate Flash Simulation, Test, Modeling and Reliability

• 16.1 Ballistic Current in Scaled FG NAND Flash (Stanford, and Intel)
• 16.2 New Program/Erase Degradation Mechnism for FG NAND at 51-31nm (Samsung)
• 16.3 Formula for Predicting RTN Instabilities in Deca-nm Flash(Numonyx, Polit.diMilano)
• 16.4 Low Freq. Noise Characteristics of 70 nm NAND Flash(Hynix, Kyungpool U,Daegu U)
• 16.5 Analysis of TID Effects on NAND Flash Circuits
• 16.6 Multilevel Cell NAND Flash System Durability Improvement
• 16.7 Study of Random Telegraph Noise with Scaling in NAND/NOR FG Flash (Numonyx)
• 16.8 Simulations of Floating Gate Cell Leakage Though High-k IPD (IMEC)
• 16.9 Neutron Caused Bit Errors in Floating Gate Flash Memories (Numonyx & STM)
• 16.10 Gate Type Independent Verification of NOR and NAND Flash Memory Cores
• 16.11 Static Trigger Wear Leveling Strategy for Flash Memory System
• 16.12 Test of Address Decoder Faults in NOR Flash Memory
• 16.13 Statistical Distribution of Random Telegraph Noise in Flash (STMicroelectronics)
• 16.14 Monte Carlo Simulator for Modeling Leakage Current in Flash Using High-k (Intel)
• 16.15 Injection Spread of Electrons in FG During F-N Programming(STM & P.di Milano)
• 16.16 Survey of Issues for Flash Memory (Ajou University)
• 16.17 Memory Tester for Flash Memory (Advantest)

17.0 Reliability Issues for Trapping Site Storage Memory

• 17.1 Effect of Edge Fringing Field Effect of STI on CT NAND Flash (Macronix)
• 17.2 Reliability Improvement in 20 nm MLC NAND Flash Planar MONOS Cell(Toshiba)
• 17.3 Resolving Fast Vth Transients After P/E of Flash Memory Stacks (IMEC&ESAT)
• 17.4 Charge Trapping Mechanisms of MONOS Flash with High Endurance(U.of Tsukuba)
• 17.5 Radiation Hardened Read Circuit for SONOS EEPROM (TsingHua Univ.)
• 17.6 Endurance Issues in SONOS Due to Degradation of Top&Bottom Oxides(Macronix)
• 17.7 Charge Granularity Effect During NOR Flash CHE Program(Politecnico di Milano)
• 17.8 Statistical Retention Study of ONO Gate Stack Scaling in 50nm FG Flash (Samsung)
• 17.9 Effect of SiN Deposition on Charge Trapping Retention and Performance (Numonyx)
• 17.10 Read Operation Using GIDL current for Dual-Bit SONOS (U. of Calif., Berkeley)
• 17.11 A Study of the Erase Mechanism of Charge Trapping Devices (Macronix)
• 17.12 Statistical Analysis of V-SILC Related Data Retention Issues in Flash (Hitachi)
• 17.13 Estimate of Uncorrectable Bit-Error Rates for NAND Flash (Micron & Intel)
• 17.14 Study of High Vt Data Retention for Hot Hole Erase SONOS (Macronix)
• 17.15 Relaxation Dynamics of Trapped Holes and Electronics in NROM ONO (Saifun)
• 17.16 Single & Bi-Layer Charge Trap Flash Reliability(Indian Inst.of Tech., Applied Mat.)
• 17.17 Interference Effects of Thin Body Double Gate Trapped Charge Flash (Macronix)
• 17.18 Impact Ionization Disturb While Programming a Neighboring Cell(Macronix)
• 17.19 Hydrogen Diffusion/Invasion in Nitride Trapping Flash Memory (Macronix)

18.0 Modeling and Simulation for Trapping Site Memories

• 18.1 Simulation of Electron Trap Energy in High-K for Flash (IMEC,John Moores U)
• 18.2 Charge Trap Mechanisms of Nitride-Based NV Memories(CEA, LETI, MINATEC)
• 18.3 Simulations for Warm Electron Injection in Double Gate SONOS (U. of Calabria)
• 18.4 Programming Mechanism Wrapped Select Gate NOR SONOS(UMC,SSS, CTU,FCU)
• 18.5 Model for Program/Erase of TANOS Flash (Numonyx & Pol.di Milano)
• 18.6 Model for Nitride Charge Trap Tri-Gate Non-Volatile Memories (CEA-LETI)
• 18.7 Warm Electron Injection Simulation in 2-Gate SONOS (U.Calabria, U.Pisa, U.Illinois)
• 18.8 Simulation to Evaluate Performance of Charge Trapping Memory (U. of Peking)
• 18.9 Model of Eff. Vertical Trap Location for Different Materials (SKKU, NUS, Fudan U.)
• 18.10 Profiling the Nitride Trap Energy Distribution in a SONOS Flash (Macronix)
• 18.11 Trapping Dynamics Using Gate/Channel Sensing Transient Analysis (Macronix)

19.0 Vendors and Developers for Standalone Flash Memory

• 19.1 Cypress
• 19.2 Hynix
• 19.3 IM Flash (Intel, Micron)
• 19.4 Intel Flash Memory Development
• 19.5 Macronix Charge Trapping Flash Memory
• 19.6 Micron (Also See IM Flash Technologies)
• 19.7 Numonyx (STM and Intel)
• 19.8 Samsung
• 19.9 SanDisk
• 19.10 Spansion (Saifun, SMIC)
• 19.11 Toshiba and SanDisk
• 19.12 Toshiba

Bibliography:

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