High Performance DRAM Course

	MEMORY STRATEGIES INTERNATIONAL Semiconductor Memory Services
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HIGH PERFORMANCE DRAM COURSE

Lecturer:	Betty Prince, Ph.D.
Author of:	Emerging Memories: Technologies and Trends, 2002, Kluwer Academic
	High Performance Memories, Revised Edition 1999, John Wiley & Sons
	Semiconductor Memories, 2nd Edition, 1992, John Wiley & Sons

Overview: This two day course in High Performance DRAMs provides background for new DRAM engineers and a refresher for current memory Engineering Staff. It focuses on the architecture, operation and applications of the fast new architecture DRAMs. Included are a review of fast access modes Fast Page and EDO, background on the architecture and operation of the various Synchronous DRAMs including SDRAM, DDR SDRAM; Rambus DRAMs; alternative architecture DRAMs such as the CDRAM, ESDRAM, MDRAM, FCRAM and VCDRAM; and the various Graphics DRAMs. DRAM modules, test, and reliability are also covered.

Day One:
9:00	Overview of Fast DRAM System Trends
10:00	Basics of Fast DRAMs (architecture, bandwidth, granularity, refresh)
11:00	Fast Access Modes in Asynchronous DRAMs
12:00	Lunch Break
1:00	SDR SDRAM Operation
2:30	DDR I SDRAM Operation
3:00	DDR II SDRAM Operation
3:30	High Speed Interfaces for DRAMs
4:00	Fast Interface DRAMs (RDRAM)
4:30	End

Day Two:
9:00	Fast Core SDRAM Concepts (ESDRAM, FCRAM, RL-DRAM, multi-bank DRAM)
10:30	Graphics DRAM Issues
11:00	Networking DRAMs (1 transistor cell SRAMs)
12:00	Lunch Break
1:00	Mobile DRAM / Low Power DRAM Issues
2:00	Fast DRAM Packaging and Modules
3:30	DRAM Test and Reliability Issues
4:30	End

To have this seminar presented at your company, please contact us at:

Memory Strategies International
16900 Stockton Drive
Leander, Texas USA 78641
Phone: 1-512-260-8226
Fax: 1-512-260-6220 <== Please Note the NEW FAX NUMBER
info@memorystrategies.com
www.memorystrategies.com

Cost:
$2600.00 per course up to10 participants. This base fee is due in advance.
$250.00 for each additional participant over 10, with maximum of 30 per course.

A binder of the seminar material is provided to each participant.
Seminar room and digital projector is to be provided by sponsoring organization.
Travel expenses for one from Austin, Texas are additional.
Attendance numbers must be provided 10 days in advance (20 days for classes outside the continental U.S.)

Cancellation Policy: Cancellations less than 31 days in advance (41 days for classes outside the continental U.S.) will be billed for any non-refundable travel arrangement expenses. To cover preparation costs, cancellations less than 10 days (20 days outside the continental U.S.) in advance will be billed a fee of $60 per person per course.

Dr.Prince is CEO of Memory Strategies International, a semiconductor memory services company in Leander, Texas, founded in 1993 and President of Processor Strategies International, a subsidiary of Memory Strategies. She has spent over 30 years in Engineering, Marketing and Operations Management in the semiconductor industry in both the USA and Europe with Texas Instruments, N.V. Philips, Motorola, RCA Semiconductor, and Fairchild Semiconductor.

She is on the Scientific Advisory Board of Cavendish Kinetics (S'Hertogenbosch, NL), and has also served on the Scientific Advisory Boards of Silicon Access Networks (U.S.A.) and Cogent Chipware (Vancouver, B.C.). She was on the Board of Directors of Mosaid Technologies (Ottawa, Canada) from 1997 to 2003.

She is author of the books, Semiconductor Memories (1982), Semiconductor Memories 2nd Edition (1992), High Performance Memories, (1996, revised 1999), Emerging Memories-Technologies and Trends, (2002), and Modern Memories to be published by John Wiley & Sons.

She is a Distinguished Lecturer and Senior Member of the IEEE and is involved in the Non-Volatile Section of the ITRS Technology Roadmap. She was a member of the EIA JEDEC JC42 Memory Standards Committee for 20 years where she served as founder and chairman of the JC16 Electrical Interface Standards Committee, Co-Chair of the JC-42.4 SRAM/CAM Standards Committee and US National Delegate to the IEC SC47 WG3 International Memory Standards Group. She has served on the Editorial Board of the IEEE Spectrum, and has given technical papers and tutorials at various IEEE conferences. She holds several patents in the semiconductor memory area.

She has a B.Sc. in Physics, an M.Sc. in Physics, an MBA in International Business and a Ph.D. in International Finance.

Memory Strategies International, 16900 Stockton Drive, Leander, TX, USA, 78641; 512.260.8226 (phone), 512.260.6220 (fax). Send questions or comments about this website to webmaster@memorystrategies.com. Copyright © 2009 Memory Strategies International. All rights reserved. Legal stuff. Last Modified: January, 2009.