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Trends in eDRAM and 3-D DRAM-in-Logic, September 2012
(1T1C eDRAM, 3D Stacked TSV DRAM Chips, FB-DRAM, Unified RAM, Logic Gain DRAM, Bipolar NPN RAM)

Embedded DRAM applications include mobile graphics, wireless, and handhelds, cache and buffer systems, parity check decoders, multicore processors with stacked eDRAM, consumer electronics and security applications.

Embedded DRAM technology has moved in four directions in the past year or so:

  1. Work continues on 1T1C eDRAMs in logic compatible technologies with development moving to vertical eDRAM cells. Companies developing in this area are noted.

    1T1C eDRAM technology development has moved from 45 nm last year to 32 nm and 28 nm this year. Both MIM and trench capacitors are used along with 4F2 cells using MIMs stacked on GAA vertical access transistors. Much effort has gone into 1T1C eDRAM reliability and test for technologies such as High-K Metal Gate, and for both MIM and Trench eDRAM. 4+ foundries join the 9+ companies in development on eDRAM.
  2. 3D Stacking using TSV and microbumps for heterogeneous processor/logic/DRAM chips is an active area of development offering small footprints, high bandwidth, and low latency. Companies developing in this area are also noted.

    3D stacking of DRAM and multicore processor chips using TSV and microbumps to form single low latency, low power, wide bandwidth, small footprint chips continues as an active area of development. The technology of these 3D TSV DRAM/Logic chips is undergoing rapid development with many companies involved in different aspects of this development. Modeling, simulation and test of these devices is ongoing covering 3D design, electrical, thermal and mechanical issues. Reliability issues are being addressed such as process variation, switching noise, decoupling capacitor strategies, temperature degradation, and High-K Metal Gate, and refresh.
  3. Floating Body 1T eDRAMs continue to have a significant level of development with several groups pursuing development of their own specialized versions of this device.

    Numerous floating body cells with vertical structures have been examined. Reliability and test issues for the FB-DRAM include: data retention time, scaling, variation issues, TID effects, among others.
  4. Transistor-based eDRAMs continue in development with improved prospects in scaled technologies.
  5. Thyristor type eDRAM cells also continue in development.

150+ pages.



Trends in eDRAM and 3-D DRAM-in-Logic, September 2012

Table of Contents

1.0 Overview of Embedded DRAM and DRAM with Logic Trends

2.0 Embedded DRAM and DRAM with Logic Applications

3.0 1T1C eDRAM

4.0 Companies Developing/Supplying with 1T1C eDRAM Chips

5.0 Foundries Developing/Offering 1T1C eDRAM

6.0 3D Stacking of DRAM/Processor Chips Using TSV and Redistribution Wiring

7.0 Floating Body DRAM/ 1T Capacitorless DRAM

8.0 Unified Memories (Non-Volatile RAMs) Using Capacitorless DRAM Technology

9.0 Logic Compatible Transistor Based DRAM Gain Cells

10.0 Embedded DRAM Cells using Thyristor/NPN Transistor Technology

11.0 Novel eDRAM Cells and Research on eDRAM Cells



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