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Trends in Embedded
DRAM, July 2014
(1T1C eDRAM, 1T/FB-DRAM, Logic Gain DRAM, Innovative eDRAMs, Hybrid SRAM/DRAM Systems)
Embedded DRAMs have over the years included traditional 1T1C DRAM cell technology including MIM and trench capacitor cells. 1T floating body eDRAMs, also known as floating body eDRAMs have also been developed along with logic gain DRAMs using conventional CMOS logic transistors. There are also novel eDRAMs. There are many advantages to using embedded DRAMs in ICs including higher density and lower static power dissipation than scaled SRAMs.
Gain cell eDRAMs use the same logic transistors used by the SRAMs but fewer of them and so offer reduced cell size. An adapted refresh timing which lowers standby power consumption was discussed along with a gain cell that saves time by eliminating write-back. Various papers discuss modifications to refresh, improvements in data retention as well as improvements in read and write performance.
Conventional 1T1C eDRAMs are increasingly being used in fast processor chips and other SoC such as in graphic chips to support the high capacity of dynamic data storage required. As these high performance chips are scaled to smaller dimensions and used at lower supply voltages, the use of eSRAMs which store data in latches, is being gradually replaced by eDRAMs which store data in capacitors. This year finds Intel joining IBM in developing an eDRAM for use in their high performance processors. Other studies of eDRAMs include modeling of various characteristics such as retention time, a study of a BIST for DRAMs that reuses refresh and discussion of a new readout method. There is a discussion of replacing SRAM with DRAM in FPGAs and discussion of a chip ID generation method using retention fails. Other studies of eDRAMs include modeling of various characteristics such as retention time, a study of a BIST for DRAMs that reuses refresh and discussion of a new readout method. There is a discussion of replacing SRAM with DRAM in FPGAs and discussion of a chip ID generation method using retention fails.
eDRAMs are used in various systems and subsystems. An in-field repair at the chip level for an eDRAM was developed. An eDRAM and ASIC mounted on a interposer which reconfigured the interconnects between the two chips was discussed for a chip on wafer on substrate application. A non-refreshing eDRAM was designed to hold data for an LDPC decoder with short access window. A 1T DRAM on FD-SOI was compared to a FD-SON (silicon on nothing) and carbon nanotube (CN) FET devices. The configuration of an L3 eDRAM cache in a 32 nm server class processor was discussed by IBM along with a communications processor which also used a trench eDRAM cache. Intel discussed its 22 nm Haswell processor in tri-gate technology which used eDRAM cache for improved graphics performance. Several SRAM-eDRAM hybrid caches were discussed.
1T-DRAMs have lower storage capacitance than conventional DRAMs so endurance or retention time is an issue which is addressed in these papers. Various characteristics of ultra-thin BOX (UTBOX) 1T-DRAM were examined. A dual port two transistor Capacitor-less DRAM was discussed which had separate write and read transistors so read could be performed without disturbing refresh or write. A comparison of the endurance using conventional and biristor mode for a 1T- DRAM was discussed. A comparison of thermal characteristics of bulk BJT 1T-DRAM and SOI planar BJT 1T DRAM was done and fast write time was shown for a 2T floating body eDRAM cell. Several cases of the use of a GaP source-drain in a 2T-DRAM were examined. A 1T DRAM cell with a trench body under the channel region was discussed. A comparison of SOI and bulk silicon floating body DRAM was done.. The effect of junction engineering of 1T-DRAMs was examined.
Several innovative eDRAM devices were explored. A 1T Ferroelectric MOSFET (FeMOS) device with DRAM-like functions was described. A scaled unified RAM which used a 1T-DRAM as RAM and a BE-SONOS charge trapping device for nonvolatile memory was discussed. An SOI Field Effect Diode (FED) DRAM was descried and analyzed using numerical simulations. The cell uses a thyristor-like mode of operation.
DESCRIPTION | TO ORDER
Trends in Embedded DRAM, July 2014
Table of Contents
1.0 Overview of Embedded DRAMs
2.0 Gain Cell eDRAMs
3.0 1T1C eDRAMs
4.0 eDRAMs in System and Subsystems / Hybrid DRAM/SRAM Caches
5.0 1T-DRAMs / Capacitorless DRAMs / Floating Body DRAMs
6.0 Innovative eDRAM Devices
DESCRIPTION | CONTENTS
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