Contents | Purchase
A Memory Strategies Focus Report
Memory Technology for the Internet of
Things (IOT), March 2015
Low Power, Low Cost, & Flexible: FeRAM, SONOS, ReRAM, MRAM
The Internet of Things is a term used for smart networks of processing
systems communicating with each other. These networks are expected to improve
smart automation in many fields including: wearable medical devices, smart RFID
tags, ultra-low power instant-on MCUs, energy-harvesting devices and neural
networks which have the potential of very high powered parallel computers. These
systems must be very low power and very low cost and, if they are to be worn,
must be flexible.
Both ferroelectic capacitors and spintronics devices have been used to back
up logic gates such as flipflops and produce MCU that retain their logic state
on power-down. The FeRAM has been used in very low power systems for some time
due to its fast switching speed, low active power and non-volatility. The lack
of scalability of the 1T1C FeRAM and its incompatibility in the wafer fab have
limited its use in this application due to the high cost technology. A new
innovation for FeRAMs is deep trench capacitors.
Single transistor FeFETs have been explored for low cost system on glass
applications. Development of HfO2-based FeFETS has the promise of wafer fab
compatibility but endurance has been limited due to parasitic charge trapping.
This technology is being intensively studied. NAND-like strings of organic FeFET
arrays have been studied for use on flexible substrates to lower cost. The
effects of domain walls in ferroelectric devices are being studied. Various
organic processes for making low cost circuits have been tried. FeFETs have been
made using nanoimprinting using an organic sheet-to-sheet process at ambient
temperature. Low cost inkjet printers have been used to make rewritable memory
for RFID tags. Co-polymer ferroelectric memories have been used as low cost
flexible transparent memory with low power operation and mechanical flexibility.
Resistance RAM (ReRAM) can be made with low cost materials such as polymer
blends and with simplified manufacturing procedures. Room temperature inorganic
filament switching ReRAMs showed good stability compared to organic ReRAM. A
flexible polymer ReRAM based on Parylene-C has low voltage switching and ON/OFF
current ratio greater than 107 at 0.01V read. A Ag/polystyrene/Ag
based conductive bridge RRAM was made. Several IGZO ReRAMs have been
investigated with high ON/OFF current ratios and low read voltage. Polymer
charge trapping memories have also been made. Ferroelectric tunnel junctions
show endurance up to 106 cycles and are being studied further.
Ferroelectric nanowires are being studied for miniaturized low power circuits.
100+ pages.
Overview | Purchase
Memory Technology for the Internet of Things (IOT), March
2015
(Low Power, Low Cost, & Flexible - FeRAM, SONOS, ReRAM, MRAM),
Table of Contents
1.0 Overview of Memory For IOT Applications
2.0 Memory Applications for the Internet of Things
- 2.1 Overview of Memory Applications for the Internet of Things
- 2.2 Energy Harvesting Sensors with Ultra-Low Power MCU
- 2.2.1 Impact Energy Harvester with FeFET Memory (Panasonic)
- 2.2.2 Fully Non-Volatile 90 nm 16b MCU and 3T SpinRAM (NEC, Tohoku U.)
- 2.2.3 Retaining States on Power-Down of Transiently Powered Computers.
(Purdue U.)
- 2.2.4 ULP MCU for Fast Wakeup Using FRAM MiniArray Architecture (TI,
TSMC)
- 2.2.5 8b MCU in Hybrid Oxide-Organic Thin Film (IMEC, KU
Leuven, Panasonic, Evonik, Holst)
- 2.3 RFID Memory Applications
- 2.3.1 Overview of the RFID Market
- 2.3.2 Plastic Organic CMOS Circuit with SRAM for RFID
- 2.3.3 Electronics RFID Memory/Logic Tags
- 2.4 Portable and Wearable Medical Devices and Networking Systems
- 2.4.1 Overview of Market for Portable Medical Devices
- 2.4.2 FeRAM ECG Processor for Wearable Health Systems (KobeU,
Rohm,Omron, JST CREST)
- 2.4.3 "Store Mostly" Health Care Systems with STT-MRAM (Kobe U., LEAP)
- 2.4.4 Wearable Bio-Monitoring With NFC and eFeRAM Memory
(Kobe U, Omron Healthcare)
- 2.4.5 Miniature Medical Devices Like Hearing Aids
- 2.5 Neural Network Systems
- 2.5.1 Artificial Synapses using a 3T-FeMEM (Panasonic)
- 2.5.1.1Artificial Synapses with 3T-FeMEM for Multishade Image
Recognition (Panasonic)
- 2.5.1.2 Artificial Synapses with 3T-FeMEM on a single crystal oxide
substrate (Panasonic)
- 2.5.1.3 3-Terminal Ferroelectric Memory for On-Chip Pattern Recognition
(Panasonic)
- 2.5.2 Evolving Spiking Networks with Variable Resistive Memories (U. of
W. of England)
- 2.5.3 Organic CoPolymer RRAM as Synapse in Neuromorphic System(CNR-IMEM)
- 2.5.4 Synaptic Behavior in Flexible IZO Transistors on Plastic Substrate
(Nanjing U, CAS)
- 2.5.5 Neuromorphic chip for efficient computation (Georgia Institute of
Technology)
3.0 Conventional 1T1R/2T2R FeRAM Characteristics, Development, Reliability
and Test
- 3.1 Conventional 1T1R/2T2R FeRAM Overview
- 3.2 Result of External Mechanical Stress on a PZT Capacitor (Texas
Instruments)
- 3.3 Ferroelectric Deep Trench Capacitors for Use in 1T1C FRAM (Fraunhofer
Inst.)
- 3.4 1T1C FRAM SA with Random and Systematic Offset Compensation (TI)
- 3.5 Reference Voltage Generation for 1T1C FeRAM (U. of Electron. Sci. &
Tech. China)
- 3.6 Ferroelectric TDDB Involving Hot Atom Damage (Purdue U.)
- 3.7 Reading a 1T1C FRAM Without Reference-Voltage Generation (Port Said U)
- 3.8 Reliability of 2T2C FRAM Embedded in 180 nm Analog Friendly CMOS(TI)
- 3.9 1Mb and 2Mb Serial FRAMs (Fujitsu)
4.0 Various System Circuits Using Low Power Non-Volatile Memory
- 4.1 Overview of System Circuits Using Low Power NVM
- 4.2 STT-MRAM-based Register File in GPUs (U. of Pittsburgh)
- 4.3 Printed Organic TFT Decoder for Fe-Memory (IM2NP UMR
CNRS, Aix MarseilleU, CEA-LITEN)
- 4.4 32b MCU SoC Using NV Logic with 100% Digital State Retention (TI)
- 4.5 Power-Gated MPU Using STT MTJ NVFF with 3us Entry/Exit Delay (Tohoku
U., NEC)
- 4.6 An 350 nA Standby MCU platform with eFRAM and 6.5us Wakeup (TI)
- 4.7 DRAM-Flash Hybrid Using FeRAM and Au Nanocrystals (Cornell U.)
- 4.7.1 Introduction to 1T Hybrid Ferroelectric and Nanocrystal NVM
(Cornell U.)
- 4.7.2 Design Considerations for FE-DRAM Flash hybrid Memory (Cornell U.)
- 4.7.3 Physical Model for DRAM-Flash Hybrid Memory (Cornell U.)
- 4.8 Design of a NV D Flip-Flop with Embedded FE Capacitor (MIT, TI)
- 4.8.1 NV D Flip-Flop with State Stored in eFE Capacitor (MIT,TI)
- 4.8.2 Design of NV D Flip-Flop with eFe Capacitors (MIT, TI)
5.0 Single Transistor Ferroelectric Memories MFIS, FeFET
- 5.1 Overview of Single Transistor MFIS and FeFETs
- 5.2 TFT FeFET Using Large Grained PZT (Seoul National University)
- 5.3 MFIS Memory Using PZT Film and TiOxNy Insulator (IIT)
- 5.4 Characterization of MFeO and MFeN Semiconductor Gate Stacks for FeFETs
(IIIT)
6.0 FeFET Memories Using HfO as a Ferroelectric Material
- 6.1 Overview of FET Memories Using HfO Ferroelectric
- 6.2 Effect of Scaling on HfO2 FeFET Performance (NaMLab,
Fraunhofer CNT, Global Foundries)
- 6.3 Endurance Limitation in HfO2 FeRAM (NaMLab, TU Dresden,
Fraunhofer, Global Foundries)
- 6.4 Ferroelectric HfO2 and Charge Trapping Hysteresis Effects
(Fraunhofer IPMS-CNT,
- 6.5 FeFET Si:HfO2 Ferro and Anti-ferro CT (Fraunhofer,
Global Foundries, NaMLab, U. of Dresden)
- 6.6 TiN-Sr: HfO2-TiN capacitors with Ferroelectric Behavior (NaMLab)
- 6.7 Silicon Doped HfO2 FeFET in 28 nm Bulk Technology (NaMLab)
- 6.8 Reliability of Thin HfO2 Ferroelectric Film (NaMLab, Fraunhofer CNT,
TU Dresden)
- 6.9 Hafnium Oxide CMOS Compatible FE (NaMLab, Fraunhofer,
IMEC,GlobalFoundries, IHM)
7.0 Ferroelectric NAND NV Memory and Domain Wall Research
- 7.1 Overview of Ferroelectric NAND NV Memory
- 7.2 Flexible NAND Organic FeMEM (KU Leuven, LAE/OME, IMEC,
Amity U., Politec di Torino, TNO-Holst)
- 7.3 Dual Channel Ferroelectric FET Memory (Panasonic)
8.0 Ferroelectric Domain Wall Motion Research
- 8.1 Overview of Ferroelectric Domain Wall Motion Research
- 8.2 Hot Atom Damage Defect Generation of Ferroelectric Domain Walls
(Purdue, TI)
- 8.3 Wake-up Effects in Si:HfO2 Ferroelectric Thin Films (U. of Technology
Dalian)
9.0 Plastic Organic Ferroelectric Memory Circuit Fabrication
- 9.1 Introduction to Plastic Organic Ferroelectric Memory Circuit
Fabrication
- 9.2 Organic FeFET with Nanostripes by Nanoimprinting (U. Catholique de
Louvain)
- 9.3 Organic Complementary SRAM and Logic on Plastic Foil
(Aix-Marseille U., IM2NP, CNRS, IM@NP, LTEN-LCEI, CEA-Grenoble)
- 9.4 Printable RFID Tags with Logic, Writable Memory and Sensors (Thin Film
Elect.)
10.0 Development and Characteristics of Copolymer Ferroelectric Memories
- 10.1 Introduction to Copolymer Ferroelectric Memory Research
- 10.2 Flexible 2T2C FeRAM with TFT and P(VDF-TrFE) Copolymer
(Micron, U. of Texas Dallas)
- 10.3 P(VDF-TrFE) Copolymer Organic FeFET and FRAM Characterization (Slovak
U.)
- 10.4 Flexible Memory Devices with a-InGaZnO TFT (Inst. of Tech., Zurich)
- 10.5 ZnO Nanowire Transistor (P(VDF-TrFE) FeRAM on Glass Substrate
- 10.6 Switching & Imprint for Poly (vinylidene fluoride-trifluoroethylene)
copolymer (E.China U)
- 10.7 Technique for Determining Data Retention in Thin VDF-TrFE cells (U.of
Appli. Sci., Jena)
- 10.8 NVM Using InZiSiO channel and organic Ferroelectric gate (KyungHee
U.)
- 10.9 Graphene-Ferroelectric Device for Multi-Valued Memory System (U. of
Texas, Dallas)
- 10.10 Polarization Switching with Pulses for Fe-(P(VDF-TrFE) Thin Film
(E China U S&T)
- 10.10 Using P(VDF-TrFE-CFE) Terpolymer for fast NV Memory (Nanjing
University)
- 10.11 Fast Switching Protocol for P(VDF-TrFE) Copolymer FeRAMs (E.China
U.of S&T)
11 Resistance RAM (ReRAM) Memories using Flexible Plastic, Polymer
- 11.1 Overview of Resistance RAM Memories using Polymer
- 11.2 Design Issues for Fast, Low Power ReRAM for IOT Applications (NTHU)
- 11.3 Resistive Memory Based on PEDOT:PSS Polymer (Changchun Inst. of Ap
Chem)
- 11.4 Room Temperature Inorganic Flexible ReRAM (Nat. Dong Hwa U)
- 11.5 Low Cost, Low Power Flexible Parylene-C RRAM (IM Peking U.)
- 11.6 Inorganic-Organic ReRAM with Uniform, Multilevel Operation (IM Peking
U.)
- 11.7 Switchable Diode Effect in Polycrystal BiNdTIO ReRAM Thin Film
(Xiangtan U.)
- 11.8 Ag/Polystyrene/Ag Conductive Bridge RAM Nano-Gap Devices (U. of
Pennsylvania)
- 11.9 IZO and IGZO Resistive RAM Memories
- 11.9.1 3-State NV Resistive Memory for a-IGZO TFT Circuits (NCTU)
- 11.9.2 High Density & Performance Logic with embedded NVM Using a-IGZO
TFTs (NCTU)
- 11.10 Ni/GeOx/TiOy/TaN RRAM on Flexible Substrate (NCTU, NTNU, IM-CAS)
- 11.11 Formation of Conducting Filaments in Planar Organic Resistive Memory
(Tsinghua U.)
- 11.12 Dynamic Response of Al2O3/polymer diode ReRAM (Institute de Telecom)
- 11.13 Double Organic Layer ReRAM with Sub-20 nA Reset Current (Peking
Univ.)
- 11.14 Organic ReRAM Using PC-Interface Memory Cell Tester (Gwangju IST,
Seoul NU)
- 11.15 Parylene-C ReRAM in 8 x 8 Cross-Point Array (Peking U, Princeton U.)
- 11.16 Conduction Mechanism in Atom Switch with Polymer Solid Electrolyte
(LEAP)
12. Charge Trapping Memory Using Plastic and Polymer Both Transparent and
Flexible
- 12.1 Overview of Polymer and Flexible Charge Trapping Memory
- 12.2 GAA Si Nanowire SONOS on Plastic Substrate (KAIST)
- 12.3 Polymer Carbon Nanotube Charge Trapping Memory (CEA, IRAMIS, CNRS,
LEM)
13.0 Ferroelectric Tunnel Junctions
- 13.1 Ferroelectric Memory with Fully Patterned Tunnel Junctions (CNRS, U.
Paris-Sud)
- 13.2 LaSrMnO3/BiFeL2/LaStMn Multiferroic Tunnel Junctions (U. of S&T of
China)
- 13.3 Write Operation Study of Co/BTO/LSMO Ferroelectric Tunnel Junction
(U. Paris-Sud)
- 13.4 Compact Model for Co/BTO/LSMO Ferroelectric Tunnel Junction (FTJ)
(U of Paris-Sud)
14.0 Low Power and Plastic Memory Materials Research
- 14.1 Overview of Low Power and Plastic Memory Research
- 14.2 Improving Endurance in Fe PZT by Adding Bi-Layered SBT (Chiang Mai
U.)
- 14.3 Hybrid FeFlash Memory Cell (Seoul National University)
- 14.4 FeFETS Using Multi-Walled Carbon Nanotubes (Xiangtan U.)
- 14.5 Carbon Nanotube TFT Transistors with BNdTiO Gate (Yunnan Normal U,
Xiangtan U)
- 14.6 Low Energy Polarization Reversal of Thin Ferrelectric Nanowires(U. of
South Florida)
- 14.7 Temperature Dependence of Imprint in P(VDF-TrFE) Copolymer (Shanghai
U. Eng.Sci.)
- 14.8 Coercivity & Exchange Bias of Bismuth Ferrite NP Isolated by Polymer
(Ind. Inst.Sc.E&R)
- 14.9 Resistive Switching in Au/pentacene/Si-nanowire Arrays (Nat. Changhua
U. of Ed)
- 14.10 Resistive Switching in Multiferroic Thin Films (ChemnitzU,
UofES&T Chengdi, IofI NanoDresden)
- 14.11 Polyaniline-FeO Nanoparticle Organic NVM Device with
Magnetoresistance (NUS)
- 14.12 FE Properties of Diisopropylammonium Bromide (S.E.U of.Nanjing, U.of
Washington)
- 14.13 Phase Separated Polymer (PCBM) Ferroelectric Memory (KAUST)
Bibliography:
Overview | Contents
To order
"Memory Technology for the Internet of
Things (IOT), March 2015"
Contact
Memory Strategies or
Send us the information requested below by e-mail, fax, or post along
with your check,
bank transfer, or purchase order for $975. ($850
if a Memory Technology Report has been ordered from Memory Strategies in the
past year.)
ORDER FORM: Please send ______ copies of "Memory
Technology for the Internet of Things (IOT), March 2015" to:
| Name: |
Email: |
| Fax: |
Phone: |
| Company: |
| Address: |
| |
| |
| |
| Comments, Payment Information, etc.:
|
Report Format
____ PDF. Will be sent by email. Please send your order by email, if possible.
Printing hardcopy from PDF is permitted.
Submit Order and Payment
Information via:
Email:
info@memorystrategies.com, or
Fax: +1 512 900 2846
Post:
Memory Strategies International,
16900 Stockton Drive,
Leander, Texas 78641, U.S.A.
To pay
by:
- Credit Card: please fax credit card information to +1 512 900 2846
- Bank Transfer:
please send in your order and request
transfer details.
- Purchase Order: submit
purchase order details with order.
For more information, please Contact
Memory Strategies
| Home | Reports
| Seminars | Consulting
| Contact Us | About Us
|
Memory Strategies International, 16900 Stockton Drive, Leander, TX, USA,
78641; 512.260.8226 (phone), 512.900.2846 (fax). Send questions or
comments about this website to webmaster@memorystrategies.com.
Copyright © 2015 Memory Strategies International. All rights reserved. Legal stuff. Last Modified:
June, 2015.
