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Magnetic RAM (MRAM) and Spintronics Memory in Logic
(I. Applications & Chips, II. Modern MRAM Technologies)

April 2014

The first part of this report is dedicated to applications being actively investigated for the various MRAM technologies. Non-volatile SRAM circuits that can be used in processor chips for various levels of cache are discussed as well as NV-Flipflops, Look-up-Tables, and other NV logic circuit elements using MRAM technology. These circuits can provide instant on and off with retention of logic levels. The MRAM technology is CMOS compatible and can be added in the BEOL.

The second part of this report is devoted to the technology, device and design issues of the several types of MRAM technologies currently under investigation as well as test, reliability and modeling efforts Novel MRAM technologies are also covered. The early field programmable MTJ MRAM technology is fairly mature and in moderate volume production in applications that can use its extended temperature and radiation hard characteristics such as automotive and industrial applications. It is written using toggle mode. Its large write current makes it unsuitable for some applications. Thermal assisted MTJ MRAM technology is also in early production and has a applications that can use its lower effective write current.

Spin-Torque-Transfer (STT) MTJ MRAM technology has lower write current than the field programmable MRAM and has recently entered prototype production at at least one company. The two write directions are asymmetric. The two terminal STT-MRAM has the drawback that the read and write current use the same path which can lead to read disturb issues. The higher current write can damage the tunneling layer.

Three terminal domain wall write STT MTJ circuits have been studied recently. These circuits trade off a slightly larger cell area than conventional STT MRAM with separate read and write paths which improve the circuit reliability. The racetrack MRAM uses its shift register like characteristics to provide very fast read coupled with high density data storage.

STT-MRAM that has perpendicularly magnetized MgO-Based MTJ have also been extensively investigated and show switching speeds in the picosecond range. The perpendicular materials with bulk magnetic anisotropy (PMA) are expected to be useful for scaled technology nodes down to 15 nm. There is a significant amount of effort currently in modeling and simulating this technology and investigating its usage in Memory-in-Logic applications where it provides significant standby power reduction in circuits such as NV Flip-Flops and other latch types of circuits.

Spin Orbit Torque (SOT) MRAM technology is just in the beginning stages of development. Models and simulations are being conducted and the exact mechanisms used in write are being studied. The SOT MRAM is a three terminal device that has the advantage of separate read and write paths. It also avoids the issues involved in domain wall motion. This mechanism is thought due to either or both the Rashba effect or the Spin Hall Effect.

170+ pages.

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Table of Contents - Magnetic RAM & Spintronics Memory in Logic, April 2014

Part I : Current and Projected Magnetic RAM Applications

1.0 Overview of Prospective MRAM Applications

2.0 MRAM Replacements for Embedded SRAM and MRAM Cache

  • 2.1 Fast 1Mb 6T2MTJ Cell STT-RAM with Background Write (Tohoku U., NEC)
  • 2.2 1Mb PMA STT-MRAM Cache Memory With Low Active Power (Toshiba)
  • 2.3 A 1 Mb STT-MRAM For NV SRAM with 1.5ns Wake-up (Tohoku U.)
  • 2.4 250 MHz 1Mb PMA STT-MRAM for embedded cache in MPU (Toshiba)
  • 2.5 An STT-MRAM circuit for L2 SRAM cache (Toshiba)
  • 2.6 Fast 1T1MTJ Cache Using Asymmetric Write Characteristics of Cell (Purdue U.)
  • 2.7 Technique to Reduce Write Energy in an STT-RAM Cache (Kobe U.)
  • 2.8 Memory for Large L3 Cache (U. of Maryland)
  • 2.9 Low Power MRAM to Replace SRAM (Qualcomm, IMEC)
  • 2.10 MRAM-SRAM Cache with Reduced Write Penalties (U. of Pittsburgh)
  • 2.11 Using STT-MRAM as Input Buffer for Network-on-Chip Processor (Texas A&M U.)

3.0 TCAM Applications

  • 3.1 Two NV CAM Cells Configured with MTJ and CMOS Transistors (Northeastern U.)
  • 3.2 4T-2MTJ Cell for Fully Parallel Non-Volatile TCAM (Tohoku Univ., NEC)

4.0 Big Memory Applications

  • 4.1 RAID Storage Systems (Everspin)
  • 4.2 MRAM Cache in SSD (Everspin)
  • 4.3 DRAM as Main Memory (Penn State Univ.)

5.0 Adaptive Processing

  • 5.1 Variable NV Memory Arrays for Adaptive Computing (Toshiba)

6.0 Automotive Applications

  • 6.1 Engine Control Units at Extended Temperature (Everspin)

7.0 Medical Applications

  • 7.1 Store Mostly Health Care Systems (Kobe U., LEAP)
  • 7.2 Automated Diagnostic Chip Using MTJ Arrays (TI of Phys. & Chem., CAS)

8.0 Industrial Applications

  • 8.1 VME Board Critical Data Storage (Everspin)
  • 8.2 1Mb MRAM with Quad SPI Interface (Everspin)

9.0. Mobile Phone MRAM Applications

  • 9.1 Perpendicular MTJ (p-MTJ) MRAM in Mobile CPU Applications: (Toshiba)
  • 9.2 Power-Gating for Low Power, Fast Write p-MTJ Mobile MRAM (Toshiba)
  • 9.3 A DRAM/MRAM hybrid memory design for Fast Mobile CPU (Toshiba)

10.0 Space and Military Applications

  • 10.1 Space Applications for Radiation Induced Soft Error Immunity (Everspsin)
  • 10.2 Radiation Hardening for MRAM-Based NV Latches & Logic (U.of Paris-Sud)

11.0 Smart Cards

  • 11.1 Smart Card Chips with MLU and MRAM (Crocus, ARM)
  • 11.2 Secure MCU for Smart Card Industry (Crocus, SMIC)
  • 11.3 MCU with Embedded NV MRAM Memory and MTJ Logic

12.0 Spin-Torque Sensors in Embedded Cache Memory

  • 12.1 Spin-Torque Sensors in MRAM Cache Memory (Purdue U.)
  • 12.2 Spin-Torque Sensing for Energy Reduction in on-chip Cache (Purdue U,)
  • 12.3 90 nm 3-Terminal MTJ MCU for Low Standby Power (Sensor) Applications

13 MRAM Roadmaps and Production Lines

  • 13.1 MRAM Roadmaps
  • 13.2 MRAM Production Lines

14.0 Demonstrations of Operational MRAM Chips

  • 14.1 Device Considerations of 90 nm CMOS 64Mb DDR3 ST-MRAM (Everspin)
  • 14.2 1.6 GT/s 64Mb DDR3 ST-MRAM Operating Characteristics (Everspin)
  • 14.3 8MB STT-MRAM Operational Test Chip (TDK-Headway Technologies, IBM)

15.0 Integration of MRAM and Logic

  • 15.1 Cell-Base Design Flow for MTJ/MOS Hybrid Logic Circuits (Tohoku U., NEC)
  • 15.2 Motion Vector Prediction Circuit Using 90 nm MTJ/MOS Circuitry (Tohoku U., NEC)
  • 15.3 MTJ-Based Spin Register for NV ICs (U. of Minnesota)
  • 15.4 Self-Enabled Error-Free Switching STT-MRAM and Logic (U.Paris-Sud, IEF, CNRS, UMR)
  • 15.5 Scalable Serial Configuration for MTJ-MOS Hybrid Logic (Tohoku U.)

16.0 MTJ Logic Circuits (Shift Resister, CAM, Latch, FlipFlop, Reconfigurable Logic)

  • 16.1 NV Flip-Flop Based on Spin Orbit Torque Coupling (SPINTEC, CEA)
  • 16.2 NV MTJ Flip-Flop Using Two-Phase Write (NUS)
  • 16.3 Power-Gated MPU Using STT MTJ NVFF with 3us Entry/Exit Delay (Tohoku U., NEC)
  • 16.4 Simulation Study of a Non-Volatile Magnetic Flip-Flop (TU Wien)
  • 16.5 Reliability Simulation of MTJ-based Logic Gates Integrated in CMOS (TU Wien)
  • 16.6 Magnetic Full Adder Circuit Based on PMA STT-MRAM (IEF, U. Paris-Sud)
  • 16.7 MTJ-based Logic-in-Memory Architecture (Tohoku U.)
  • 16.8 4T-2MTJ Cell for Fully Parallel Non-Volatile TCAM (Tohoku Univ., NEC)
  • 16.9 MTJ-based Zero Standby Current Retention Flip-Flop (Yonsei Univ)
  • 16.10 Power-Gating for a NV Logic-in-Memory for Motion-Vector Extraction (Tohoku U.)

 

 

Part II. Modern MRAM Technologies

1.0 Current Status of MRAM Technologies

  • 1.1 An overview of Current MRAM Scaled Technologies (AIST, Osaka U., CREST, Toshiba)
  • 1.2 An Overview of : STT-MRAM, DW Motion MRAM and SOT MRAM

2.0 Spin Transfer Torque (STT) MRAM Device and Design

  • 2.1 Introduction to Spin Transfer Torque (STT) MRAM technology.
  • 2.2 Comparison of Four MTJ Stacks for Device & Circuit Characteristics (Vellore IT U)
  • 2.3 Methods for Improved Density & Speed of MLC STT-RAM Cache (U. of Pittsburgh)
  • 2.4 Designing STT-MRAM for Embedded Memory in a CMOS Process (Georgia Tech
  • 2.5 Minimizing Reference Resistance Distribution in STT-MRAM (A*STAR, NUS)
  • 2.6 Effect of Co50Fe50 Free Layer Thickness on MTJ (Trinity College, Inst. of Phys. CAS)
  • 2.7 Switching in SyF Layers with In-Plane Magnetization (U.Paris-Sud, UMR, CNRS, Hitachi)
  • 2.8 Reduced STT Switch Current with Non-Collinear Polarizer Magnetization (Inha U.)
  • 2.9 Switching Time with Composite Free Layer MTJ (TU Wien)
  • 2.10 Design Analysis for Scaled 1T-1MTJ STT-MRAM Memory (U. of Calif., L.A.)
  • 2.11 STT Switching Dependence on Coupling Strength in Synthetic FL MTJ (Tohoku U.)

3.0 STT MRAM Circuit Techniques

  • 3.1 Offset-Canceling Triple State Sensing Circuit for STT-RAM (Yonsei U, Qualcomm)
  • 3.2 Reference Calibration Technique for Body-Voltage Sense Circuit (U. of Calif. LA)
  • 3.3 Differential STT-RAM Cell Structure with Two Modes (U. of Pittsburgh).
  • 3.4 STT-MRAM bit cell with ROM Overlay (Purdue University)
  • 3.5 STT-MRAM Sensing Circuit with Self Body Biasing (Yonsei U., Qualcomm)
  • 3.6 Improved Endurance using Balanced Write Path for 40nm 1Mb STT-MRAM (TSMC)
  • 3.7 Voltage Driven Nondestructive Self-Reference Sensing for STT-MRAM (New York U.)

4.0 STT MRAM Device, Process and Process Techniques

  • 4.1 Low Temperature Stability of MTJ Patterned by RIE (U. of Calif. San Diego)
  • 4.2 Improved Switching Margin with 20 nm iPMA MTJ Structure (Samsung)
  • 4.3 Ballistic Elec. Magnetic Macroscope to Analyze Spin Electron Transport (U.of Groningen)
  • 4.4 Effect of MgO Spacer/Annealing Properties of NiFe/MgO/CoFe Structure(IIT, Delhi)
  • 4.5 Effect of Chemical Diffusion on the TMR of an MTJ, (Beij. Inst. of Phys CAS, Tohoku U)
  • 4.6 Engineering the MgO Interface in an STT-RAM(LEAP)
  • 4.7 Interface and Oxide Quality of CoFeB/MgO/Si Tunnel Junctions (Cornell U.)
  • 4.8 MTJ Using CoFeB/FeNiSiB FLayer(Korea U, Korea BSI, Fukushima NCT, Tohoku U, U. Calif.-SD
  • 4.9 MRAM Stack Interlayer Properties Using Ferromagnetic Resonance (New York U.)
  • 4.10 Multi-step Ion Beam Etch of <30 nm p-MTJ (HanyangU)
  • 4.11 MTJ Microstructure & ElectroMagnetics with Naturally Oxidized MgO (LEAP)
  • 4.12 Room Temp MR in Ion Beam Sputtered CeFeB/SrTiO3/CoFeB MTJ (CEA, LETI, MINATEC, SPINTEC, UMR,CNRS, UJF, CEA0INAC, SPTS, U. of Puerto Rico)

5.0 Issues with STT MRAM

  • 5.1 Read Disturb in an STT MRAM
  • 5.1.1 Pulsed Read for 1T1R STT-MRAM to Reduce Read Disturb (Georgia Inst. of Tech.)
  • 5.1.2 3-Terminal MTJ Memory Cell with Read Disturb Immunity (U. of Toronto)
  • 5.1.3 Time Differential Sense Amp for 40 nm STT MRAM (Infineon, TU Munich)
  • 5.2 Increasing Switching Speed in STT MRAM
  • 5.2.1 Fast Switching in MTJ with Two Pinned Layers (TU Wien)
  • 5.3 Decreasing Switching Current Density in an STT-MRAM
  • 5.3.2 Multilayer MTJ with Low Current & High Stability(KoreaU, NIST, UofMaryland)
  • 5.3.3 Thin B Layer in MTJ CoFeB Free Layer to Reduce Current Density(IBM, U.ofTokyo)
  • 5.4 Source Degeneration Effect and Current Asymmetry Issue in STT MRAM
  • 5.4.1 Area Efficient Design Based on MTJ Current Switching Asymmetry (Tohoku U)
  • 5.5 Thermal Stability Issues in STT MRAM
  • 5.5.1 Spin Torque Assisted Thermal Switching of a Free Layer (NIAIST)
  • 5.5.2 Effect of Self-Heating on the Reliability of an STT-RAM Cell (Georgia Inst. of Tech)

6.0 Multiple Level/State STT-MRAM

  • 6.1 Fast Read 1T2MTJ MLC STT-MRAM with Stacked Perpendicular MTJ (LEAP)

7.0 Domain Wall STT MRAM Cell Technology

  • 7.1 Multi-Level MRAM using Domain Wall Shift for a High Density Cache (Purdue U.)
  • 7.2 FeCo-oxide as a Magnetic Coupling Layer in an mLogic Cell (Carnegie Mellon U.)
  • 7.3 Multi-Level MRAM Cell Based on Domain Wall Shift Storing 2b per Cell (Purdue U.)
  • 7.4 DW Motion MRAM With PMA (Renesas, Tohoku U., NIMSA Tsukuba)
  • 7.5 Domain Wall Memory with Shift Based Writes for Use in a Cache Hierarchy (Purdue U.)
  • 7.6 Domain-Wall-Assisted Switching of Single-Domain Nanomagnets (U. of Notre Dame)
  • 7.7 Spin-Wave Excitations in a Confined Domain Wall (AIST)
  • 7.8 Domain Wall Transfer Via Graphene Electrostatic Control (N. Carolina State U)
  • 7.9 Notch Shape Effect on Domain Wall Motion in Nanowires with IMA or PMA(KoreaU)
  • 7.10 Domain Wall Motion Cell with PMA Wire and In-Plane MTJ (NEC)

8.0 Racetrack Type Domain Wall Memory-Logic

  • 8.1 Domain-Wall Nanowire Memory for Memory and Logic (Nanyang TU)
  • 8.2 STT Driven Magnetically Coupled DW Shift Register memory (Carnetie Mellon U.)
  • 8.3 Magnetic Adder based on a Vertical Racetrack Memory (U. of Paris-Sud, UMR8622m CNRS)
  • 8.4 A PMA CoFeB Racetrack Memory (U. of Paris-Sud)

9.0 Three Terminal STT-MRAM Mechanism and Cells

  • 9.1 Compact Model of 3 Terminal MRAM Switching (SPINTEC, UNR, INAC, CEA/CNRS/UJF)
  • 9.2 Complementary Polarizer Cell to Improve Sense Margin and Read Disturb (Purdue U.)
  • 9.3 Scaling Factors for Three Terminal DWM Cells (Tohoku U.)
  • 9.4 Non-Local STT-MRAM Using Non-Local Spin Injection for Write (PurdueU., Intel)
  • 9.5 Three Terminal DWM Device for eMemory (TohokuU, KyotoU, PRESTO, NEC, Renesas)

10.0 MRAM with Spin Transfer Write and Perpendicular Anisotropy

  • 10.1 <1ns Switch & <20nm Scaling(SPINTEC, UMR, CEA/DSM/INAC-CNRS/UJF-G-INP, Crocus, SP2M/NM,ISCDG)
  • 10.2 A Top Pinned PMA MTJ with Counter Bias Field to Suppress Stray Field (LEAP)
  • 10.3 Optimization of Co/Pd Multilayer-based Reference Layers in p-MTJ (IBM)
  • 10.4 Impact of Pinned Layer Stray Field on Switching Properties of PMA-MTJ (ITRI)
  • 10.5 Tilting Pinned Layer MA of MTJ to Reduce Switching Current (Purdue)
  • 10.6 PMA MTJ STT-MRAM with Dummy Free Layer and Dual Tunnel Junctions (LEAP)
  • 10.7 PMA of Co20Fe50Ge30 Induced by the MgO Interface (U. of Virginia)
  • 10.8 Effect of Mg interlayer on PMA of MgO/Mg/CoFeB/Ta Structure(Tohoku U.)
  • 10.9 PMA Induced by a Nb Cap Layer in thin MgO/DoFeB/Nb (Nat. Chung Cheng U.)
  • 10.10 Thin Pt Layer on Ru in SAF with PMA (SPINTEC, UMR, CEA/CNRS, UJF, INP, CEA/INAC
  • 10.11 Optimizing Ta Thickness for PMA MTJ in MgO-FeCoB-Ta System(Carnegie Mellon U.)
  • 10.12 Perpend. Magnetization of Co20Fe50Ge30 Films Induced by MgO (U.of Virginia)
  • 10.13 Low magnetization alloys for in-plane STT devices(Trinity Col., Marmar U., Calik Holding)
  • 10.14 Precessional Switching for MRAM with Perpendicular Polarizer(SPINTEC, UMR CEA/
  • CNRS/UJF/INP/INAC, U. Paris-Sud, Crocus Tech., SP2M/NM) IMW)
  • 10.15 Co/Ni Multilayers with Post-Annealing PMA(SPINTEC,UMR,CEA/CNRS/UJF/ INP, INAC)
  • 10.16 Reduce Interdiffusion to raise PMA in Co/Pt (SPINTEC,UMR, CEA/CNRS/UJF, INP, INAC)
  • 10.17 Size Dependence of STT Switching in CoFeB p-MTJ (IBM-MagIC)

11.0 Topics and Issues in Perpendicular MTJ MRAM

  • 11.1 Thermal Stability Factor in CoFeB/MgO MTJ MRAM
  • 11.1.1 STS of pMTJ CoFeB-Based Tunnel Junctions with High Thermal Tolerance (Sony)
  • 11.1.2 MTJ Thermal Stability Factor of Single & Double CoFeB-MgO Interfaces (Tohoku U)
  • 11.1.3 Scalability to < 20 nm Node Using Dual Interface PMA MTJ (Samsung, Grandis)
  • 11.1.4 Free Layer Thickness Vs. Thermal Stability Factor in CoFeB/MgO (Tohoku U,. Hitachi)
  • 11.2 Electric Field Effect and Voltage Pulse Switching of Perpendicular Magnetized MTJ
  • 11.2.1 Voltage-Induced Switching of Nano MTJ (U.of California, L.A.&Irvine, Hitachi, Singulus)
  • 11.2.2 Pulse Voltage Induced Dynamic Switching in MTJ with High RA (Osaka U.)
  • 11.2.3 Field Induced Magnetization Reversal in CoFeB-MgO MTJ (Tohoku U.)
  • 11.2.4 Electric Field Control of MA in CoFeBO/oxide Stacks at Low Voltage (IBM)
  • 11.2.5 Current Switching of Exchange Bias Using Current Pulses (Nat. Changhua U. of Ed.)

12.0 In-Plane vs. Perpendicular Magnetization

  • 12.1 Roadmap of Planar & Perpendicular STT-MRAM (U. of Missesota, NUS)
  • 12.2 Switching & Energy in In-Plane & PMA MTJ (U. of Calif., Irvine,U. of Minnesota, Hitachi, Singulus Tech, U. of Calif. Los Angeles, Avalanche Tech)
  • 12.3 In-Plane Compared to PMA STT MRAM Scaled To 20 nm (IBM-MagIC)

13.0 Simulation and Modeling of Spin Write MRAMs

  • 13.1 Model for TDDB of MgO in MTJ-MRAM Cell (Purdue)
  • 13.2 SPICE Compact Model for Simulating Hybrid MTJ/CMOS Circuits (Purdue U.)
  • 13.3 Simulation for STT-MRAM with Multiferroic Tunnel Junctions (Purdue U.)
  • 13.4 Multi-level STT MRAM Cell Based on Stochastic Switching (U. Paris-Sud)
  • 13.5 Modeling of Stochastic STT Write in MTJ (U. Paris-Sud, UMR, SPINTEC, CEA/CNRS)
  • 13.6 Simulated Characteristics of Lateral TMR Memory Cell (Peking U., Tsinghua U.)
  • 13.7 Energy-Delay-Reliability Write Model for PMA STT-RAM Cell (U of Virginia, Alabama)
  • 13.8 Spintronics Simulation Program Using SPICE and MTJ Models (NEC, TohokuU)
  • 13.9 A Study of STT in MTJs Using the Multi-Orbit Tight Binding Model (Inha U.)

14.0 Test, Yield and Reliability Issues for STT- MRAM

  • 14.1 Failure Mitigation Techniques for 1T-1MTJ STT-MRAM Cells (Purdue U.)
  • 14.2 Testing Resistive-Open Defects in TAS-MRAM (Crocus, LIRMM, U. Montpellier, CNRS)
  • 14.3 Reducing Read Disturb using Pulse Width Control for in-plane STT MTJ (Avalanche)
  • 14.4 Switching Failure From Transverse Domain Wall Formation in FL (TU Wien)
  • 14.5 TDDB of the MgO for an STT-MRAM (Purdue U.)
  • 14.6 STT-MRAM in 65 nm LP-CMOS with Radiation Results (U. Albany, Avalanche)
  • 14.7 Growth & Annealing Effect on MRAM Low Freq.1/f Noise (Trinity Col., U. of Delaware)
  • 14.8 MTJ Bit Error Rate Measurement at 106 writes-per-second. (Avalanche Tech.)
  • 14.9 STT-RAM Write Error Tolerant Cache Architecture (MagIC, Rensselaer, Xi'an Jiaotong U.)
  • 14.10 Barrier Breakdown Mechanisms in Pulsed Stress MgO-based MTJ (SPINTEC)
  • 14.11 STT Switching Temperature Dependence 25 C to 85 C.(U.of Minnesota)
  • 14.12 TDDB Study of MTJ with Naturally Oxidized MgO Barrier (LEAP)

15.0 Spin Orbit Torque (SOT) Devices

  • 15.1 Compact MTJ Model for Spin Orbit Torque (SPINTEC, UMR, INAC, CEA/CNRS/UJF)
  • 15.2 Rashba-Induced Spin Torque Switching
  • 15.2.1 Using Rashba Effect for Write & Read in a Single FM Layer (NUS)
  • 15.2.2 Quantum Wire Spin FET Which Detects Rashba Spin Coupling (City U of Hong Kong)
  • 15.3 Spin Hall Effect With Spin Torque Switches
  • 15.3.1 Spin Hall Effect in Fast Current Mode Spin-Torque switches. (Purdue U.)
  • 15.3.2 Differential Spin-Hall embedded MRAM (Purdue U.)
  • 15.3.3 Perpendicular Anisotropy CoFeB-MgO using Spin-Hall Effect (U.of Calif. Berkeley)

16.0 Thermal Assisted, Magnonic Write and Thermal Transport in MRAMs

  • 16.1 Thermal Assisted MRAM Production (Crocus)
  • 16.2 Scalability & Logic Func. of TA-MRAMs (SPINTEC CEA-INAC/CRNS/UJF/G-INP, Crocus)
  • 16.3 TA-STT Magnetic Reversal of Uniaxial Nanomagnets in Energy Space(NY U.)
  • 16.4 MTJ Storage & Logic Unit Using Thermally Assisted MRAM (Crocus, SPINTEC)
  • 16.5 Storing Data in Antiferromagnetic Layer Via Field-Cooling (Politechnico di Milano)
  • 16.6 Theory of Bidirectional Write Thermoelectric STT-MRAM Using Magnonic Current
  • 16.7 Spin-Dependent Thermal Transport by FM Thin Film(Johns HopkinsU, NTHU,Acd. Sinica)
  • 16.8 Current Direction Heating Asymmetry in TA-MRAM (SPINTEC, CEA/INAC-CNRS)

17.0 Vertical 3D MRAMs.

  • 17.1 MRAMs in Cross-Point Arrays
  • 17.1.1 Diode-MTJ Cross-Point Memory Using Unipolar Switching (U.of Calif,Hitachi, Singulus)
  • 17.1.2 Cross-Point Architecture Using STT-MRAM (IEF, U.Paris-Sud, UMR, CNRS, STMicro.)
  • 17.1.3 High Density Cross-Point STT-MRAM Architecture (U. Paris-Sud)
  • 17.2 3-D Folded STT-MRAM Cell Using In-Plane Magnetic Anisotropy Materials (Samsung)

18.0 Field Switching MRAMs

  • 18.1 Neutron Radiation Effect on Toggle Mode MRAM (LIRMM, U. de Montpellier)
  • 18.2 Write Current Self-Configuration Method (NTHU)
  • 18.3 Write Current Self-Configuration for MRAM Yield Improvement (NTHU)

19.0 MTJ MRAM Materials and Device Research Issues

  • 19.1 Voltage Driven Magnetization Switching (AIST, Osaka U.)
  • 19.2 Temperature Dependence of Jo for STT TA-MRAM using GdFeCo(Nagoya U, NISRI
  • 19.3 A Study of Coupled Spin Torque Nano Oscillators (U. of Virginia)
  • 19.4 Design and Operation of Pseudo-Spin MOSFET (Tokyo Inst. of Tech, U.of Tokyo)
  • 19.5 Quantized Spin Wave Excited in an MTJ (AIST)
  • 19.6. Hybrid Spintronic/Straintronics Computing System (Virginia Commonwealth)
  • 19.7 Planar Arrays of Magnetic Nanocrystals Embedded in GaN (Johannes Kepler U.)
  • 19.8 Vanadium-doped LiNbO3 Structure and Ferromagnetism (Tsinghua Univ.)
  • 19.9 Precessional Reversal in Orthogonal STT-MRAM (New York Univ.)
  • 19.10 Magnetic Vortex Core Switching for MRAM (Ghent U., Max Planck Inst.)

20.0 Graphene, Nanoribbons and Edge Conductors in Spin Devices

  • 20.1 Graphene Based MTJ (Naval Research Lab)
  • 20.2 Long Diffusion Length Spin Transport in Graphene (CNRS/Thales, U. of Paris-Sud)
  • 20.3 Exchange Bias Dynamic Response in Graphene Nanoribbons (KU Leuven)
  • 20.4 Edge Channel Transport in Insulators attached to Ferromagnetic Leads (NUS)
  • 16.11 Configurable MRAM Logic Block Cross-Bar Technology(IEF,U.Paris-Sud,UMR, CNRS)
  • 16.12 6-Input LUT Circuit Using Series/Parallel MTJ in an FPGA (Tohoku U.)

Bibliography

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