Vertical Memory and 3D Memories, November 2009

	MEMORY STRATEGIES INTERNATIONAL Semiconductor Memory Services
\| Home \| Reports \| Seminars \| Consulting \| Contact Us \| About Us \| Site Map \| Links \|

CONTENTS | TO ORDER

Vertical and 3D Memories, November 2009
(Vertical Channels and Pillars, Double Gates, Cross-Point Stacks, 3D Stacking with TSV, Single Crystal Stacking, Vertical NAND Strings, Inductive Coupling, multiple substrate integration)

This report on vertical and 3-D memories traces the emerging trend of using the vertical dimension on the memory chip rather than doing increasingly difficult scaling in the planar dimension. Vertical pillar memories are discussed followed by vertical channels and double and triple gates. Cross-point stacked memories show promise of multiple layers of stacking in the fabrication process as do vertical NAND strings which use pillars and vertical stacks in various combinations. Through silicon vias permit stacking of varying types of substrates such as memory and processors. Some effort in inductive coupling between stacked layers is traced followed by discussion of other multiple substrate integration. 60+ pages.

DESCRIPTION | TO ORDER

Vertical and 3D Memories, November 2009

Table of Contents

Executive Summary

1.0 Vertical Pillar Gates

1.1 3D Flash Using Gate-All-Around SONOS memory with Vertical Si Nanowire (A-Star)
1.2 3D NVM in a Twin- Bit Pillar Structure with Common Control Gate (Seoul Nat. Univ.)
1.3 Bit-Cost Scalable Floating Pillar ONON Flash Memory (Toshiba)
1.4 High-k Al2O3 as Blocking Oxide for 3-D Self-Assembled NC Memory (U. of Texas)
1.5 Gate-All-Around Vertical NC Flash Cell (U. of Texas, Austin)
1.6 Vertical Flash Memory with SiGe Nanocrystals Grown on a Pillar (U. of Texas)
1.7 50 nm Node Surrounding Gate Transistor NOR Flash (Tohoku U.)

2.0 Vertical Channel Gate, Double Gate and FinFET Memories

2.1 Dopant Segregated Schottky Barrier SONOS NOR Flash (KAIST, EECS, ETRI)
2.2 Vertical Double Gate Floating Body Device (Intel)
2.3 Sub 50 nm Vertical Channel Double Gate Multi-Bit NOR Flash (Intel)
2.4 Double Gate and Tri-Gate FinFET Si-NC 10 nm Memories (STM, CEA-LETI)
2.5 Optimal Cell Structures for Scaling FB-DRAMs to 25 nm Technology (Purdue U.)
2.6 Tri-Gate FinFlash SN Memory (CEA/LETI)
2.7 Vertical FinFET Structure for Nanocrystal Memory (Samsung)
2.8 50 nm Vertical Channel Double Floating Gate NOR Flash Cell (Intel, Stanford)
2.9 50 nm Double Gate 64 Cell 3D TFT SONOS (Schiltron)

3.0 3-D Stacking of Memory using Through Silicon Vias (TSV)

3.1 Multistrata DRAM Stacked Fast CMOS Logic Using TSV and Organic Interposer (NEC)
3.2 3D Stacking of eDRAM L3 Cache over Processor with TSV (IBM)
3.3 8-Gb DDR3 SDRAM Using TSV (Samsung)
3.4 Fabrication of TSV for Stacked Memory Chips(Tohoku University)
3.5 3D Reconfigurable Logic Block with SPRAM with TSV (Hitachi and Tohoku Univ.)
3.6 3D Stacking of MRAMs on Chip Multiprocessors (Penn State Univ.)

4.0 Integrated Process Stacking of NAND Chains

4.1 Bit-Cost Scalable Floating Pillar Vertical SONOS NAND Flash Memory (Toshiba)
4.2 Vertical SONOS String and Vertical FET for BiCS NAND Flash (Toshiba)
4.3 Damascened Metal Gate SONOS Vertical NAND Flash String (Samsung)
4.4 Vertical Stacked Array with PIPE Process for Vertical NAND Chains (Samsung)
4.5 3-D NAND Flash SONOS Using Planarized Integration (Samsung, UCLA)
4.6 3-D Stacked 45 nm NAND Flash using Single Crystal Silicon Stacking (Samsung)
4.7 Stacked Bandgap Engineered TFT NAND SONOS Flash (Macronix)
4.8 3-D Stacking of NAND Flash Using Single Crystal Silicon Layers (Samsung)

5.0 Stacked Cross-Point Cells

5.1 Cross-Point PCM Using Polysilicon Selection Diode (Hitachi)
5.2 Phase Change Memory Cross-Point Cell with Doped Ge Nanowire Diodes (Stanford)
5.3 Eight Layer Stack of Cross-Point ReRAM Cells (Fudan Univ.)
5.4 Physical model for PCM with Diode Access Device (HKUST)
5.5 Vertical Cross-Point NiO Transition Metal Oxide RRAM (Samsung)
5.6 Improved Conduction Path Confinement for 3D NiO ReRAM Cell (Stanford U.)
5.7 Characterization of NiO RRAM in Low Resistance State (Politechnico di Milano)
5.8 Model for Physical Switching Mechanism in NiO Memory (Politechnico di Milano)
5.9 Stacked 3-D NiO RRAM with CuO diode and GIZO peripheral TFT (Samsung)
5.10 3-D Cross-Point Memristor Technology (Hewlett-Packard Labs)
5.11 Stacked Cross-Point Diode Ti Doped NiO RRAM Array (Samsung)
5.12 Four-Bit MRAM Cell using Two Stacked MRAM Cells (MagLabs)

6.0 Integration of Memory in the Interconnect Structure

6.1 SiO ReRAM in SiO with Cu and W Electrodes (Peking U. & U.of Calif, Riverside)
6.2 Solid Electrolyte Switch Embedded in Copper Interconnect (NEC)
6.3 Integration of NiO Memory Structures in Interconnect Structures (U. of Sud Toulon)
6.4 ReRAM Made with NiO Doped with Ti:NiO (Fujitsu)

7.0 Memory Stacking Using AC Inductive Coupling

7.1 SRAM & Processor Integration Using Inductive Coupling (Renesas, Hitachi, Keio U.)
7.2 Stacked MPU/SRAM Inductive Coupled by Through Wire (Hitachi, Renesas, Keio U)

8.0 Chip Stacking using Configurable Memory

8.1 Configurable SRAM Stacked with Various SoC Chips (NEC)

9.0 Wafer Level 3D Integration of separate substrates

9.1 Overview of 3D Wafer Bonding Technologies for Advanced Stacking Systems (ITRI)
9.2 Wafer Level 3D Integration using Adhesive Injection (Tohoku University)

10.0 Companies Developing and Supplying Vertical Memories

10.1 Fujitsu
- 10.1.1 ReRAM Made with NiO Doped with Ti:NiO (Fujitsu)
10.2 Hitachi
- 10.2.1 Cross-Point PCM Using Polysilicon Selection Diode (Hitachi)
10.3 IBM
- 10.3.1 3D Stacking of eDRAM L3 Cache over Processor with TSV (IBM)
10.4 Intel
- 10.4.1 65 nm Floating Point Processor and SRAM Using 3D Interconnects (Intel)
- 10.4.2 50 nm Vertical Double Floating Gate Multi-bit NOR Flash Cell (Intel, Stanford)
10.5 Macronix
- 10.5.1 Stacked Bandgap Engineered TFT NAND SONOS Flash (Macronix)
10.6 NEC
- 10.6.1 DRAM Stacked with Fast CMOS Logic Using TSV and Organic Interposer (NEC)
- 10.6.2 Multistrata DRAM with Stacked CMOS Using TSV and Organic Interposer (NEC)
10.7 Renesas/Hitachi
- 10.7.1 SRAM & Processor Integration Using Inductive Coupling(Renesas, Hitachi, Keio U.)
- 10.7.2 Stacked MPU/SRAM Inductive Coupled by TSV (Hitachi, Renesas, Keio U)
10.8 Samsung
- 10.8.1 3-D NAND Flash SONOS With Vertical Recess Array Transistor (Samsung, UCLA)
- 10.8.2 3-D Stacked 45 nm Floating Gate 4-Gb NAND Flash Memory (Samsung)
- 10.8.3 3-D Stacking of NAND Flash Using Single Crystal Silicon Layers (Samsung)
10.9 ST Microelectronics
- 10.9.1 Double Gate and Tri-Gate FinFET Si-NC 10 nm Memories (STM, CEA-LETI)
10.10 Toshiba
- 10.10.1 Bit-Cost Scalable Floating Pillar ONON Flash Memory (Toshiba)

11.0 Research Cooperatives and Labs Working with 3D Technology

11.1 IMEC TSV Stacking
11.2 A-Star 3D Flash Using Gate-All-Around SONOS with Vertical Si Nanowire
11.3 KAIST, EECS, ETRI - Dopant Segregated Schottky Barrier SONOS NOR Flash
11.4 CEA/LETI - Tri-Gate FinFlash SN Memory
11.5 Hewlett-Packard Labs
- 11.5.1 3-D Cross-Point Memristor Technology (Hewlett-Packard Labs)
11.6 MagLabs
- 11.6.1 Four-Bit MRAM Cell using Two Stacked MRAM Cells (MagLabs)
11.7 Schiltron
- 11.7.1 50 nm Double Gate 64 Cell 3D TFT SONOS (Schiltron)
11.8 Rensselaer Poly-Lowered Memory Wall in Fast, Multicore Processor Memory Stacks
11.9 ITRI 3D Lab for Development of TSV

Bibliography

DESCRIPTION | CONTENTS

To order "Vertical and 3D Memories, November 2009":

Contact Memory Strategies or
Send us the information requested below by e-mail, fax, or post along with your check, bank transfer, or purchase order for $975. ($850 if a Technical Market Analysis has been ordered from Memory Strategies in the past year.)

ORDER FORM:
Please send ______ copies of "Vertical and 3D Memories 2009" to:

Name:	Email:
Fax:	Phone:
Company:
Address:



Comments, Payment Information, etc.:

Report Format

____ PDF. Will be sent by email. Please send your order by email, if possible. Printing hardcopy from PDF is permitted.

____ (Hardcopy of report only available for shipping within USA. We apologize for any inconvenience.
Report will be sent by 2-Day FedEx. Please send all information requested above.)
If you wish both PDF and Hardcopy, please add an additional USD200 to your order

Submit Order and Payment Information via:
    Email: info@memorystrategies.com, or
    Fax:    +1 512 260 6220
    Post:
        Memory Strategies International,
        16900 Stockton Drive,
        Leander, Texas 78641, U.S.A.

To pay by:

Credit Card: please fax credit card information to +1 512 260 6220
Bank Transfer: please send in your order and request transfer details.
Purchase Order: submit purchase order details with order.

For more information, please Contact Memory Strategies

Memory Strategies International, 16900 Stockton Drive, Leander, TX, USA, 78641; 512.260.8226 (phone), 512.260.6220 (fax). Send questions or comments about this website to webmaster@memorystrategies.com. Copyright © 2010 Memory Strategies International. All rights reserved. Legal stuff. Last Modified: May, 2010.