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Vertical (3D) Memories, April 2012
(Vertical Channels & Pillars, FinFet, Tri-Gate, Double Gate, Cross-Bar Arrays, 3D Stacking with TSV, 3D TSV Configuration, Single Crystal Stacking, Vertical NAND Strings, Inductive Coupling )

This report on vertical and 3-D memories traces the emerging trend of using the vertical dimension on the memory chip rather than doing increasingly difficult scaling in the planar dimension.

Section 1:Three dimensional memories have been made for some time using vertical pillar gates. These include the surrounding gate, or gate-all-around flash memories. Vertical pillar flash memories are made using a SONOS deposition process and also using a nanocrystal self assembly process. Phase change memories are made with vertical acess device. 4F2 DRAMs are made with vertical pillar transistors. Dual pillar vertical STT-MRAMs are also being developed.

Section 2: FinFETs with thin vertical channels provide density and multiple bits in a small area. They are in advanced development for use in SRAMs. They have been used in floating body 1T-DRAM development and in floating gate and SONOS flash development. They improve short channel effects and increase the density of both non-volatile memories and SRAMs. Multigate nanowire memories are also in development as charge trapping flash memories of both the SONOS and nanocrystal types. There is indication FinFETs will enter production between 22nm and 14 nm.

Section 3: Double gate devices have improved gate control in scaled devices. Several vertical double gate SONOS devices have been discussed along with a double gate SONOS device in which the second gate was common to several devices. A vertical bridge NV cell used electrical isolation by a vertical pn junction. A hybrid dual gate TFT memory was suggested for large area electronics on flexible substrates. A double heterojunction bipolar transistor capacitorless 1T DRAM with a narrow bandgap SiGe body was also discussed along with a hybrid ferroelectric and Charge based NV memory.

Section 4: Nanowire high density memories can be stacked as 3-D NAND Flash. Junctionless GAA SONOS silicon horizontal nanowire was stacked as well as with vertical silicon nanowire.

Section 5: NAND chains have been stacked as pipes, as vertical trenches and through hole structures, with shield layers. Extended sidewall control gates have been added on vertical stacked NAND structures with separated sidewall control gates. Thin body charge trapping vertical gate NAND flash devices have been shown with improved sensing. Horizontal channel with vertical gate BE-SONOS NAND flash devices have been stacked with self-aligned PN diodes on the source side and also without the PN diodes. A hybrid 3D NAND flash cell with low address selection for stacked channels were shown which were suitable for NAND page operation.

Section 6: Several types of cross-bar array memories have been discussed. An electromechanical diode cell was shown, as was a CMOS memristor cross-bar array for neuromorphic architectures An organic memory cross bar array had graphene electrodes. A ZnO RRAM crossbar array was studied for sneak current.

Section 7: This section discussed memories which can be embedded in the interconnect structure normally in the back end of the line.

Section 8: Through-Silicon-Via (TSV) technology is proving it can provide high density memory arrays without the need for scaling the technology. These TSV connections appear key to future 3-D integration of substrates. Two approaches are currently being explored. One is "via-middle" schemes in which TSV are formed after the transistors are made but before BEOL processing. These vias have diameters from 5 um to 10 um with aspect ratios > 10:1. The other approach is the "via-last scheme" where TSVs are etched from the back side of a thinned wafer after BEOL completion. These vias are > 40 um with aspect ratios < 10:1. Chips connected with TSV can bring significant memory bandwidth in a small footprint for handheld tablets and smart phones. This can implement software applications such as HD Video, 3D Gaming, computing and image processing. This bandwidth can be provided by Through-Silicon Via (TSV) technology which connects the DRAM I/O vertically through the silicon with the processor bus in a processor-DRAM chip stack. TSV technology reduces connection capacitance and connection length. 124]

Section 9: Memory and processor stacking using inductive coupling connects is discussed.

Section 10: TSV stacked memory system require a different architecture configuration from standalone memory and processor chips in order to make the best use of the many high bandwidth connections. A 3.9 DGIP/W TSV stacked SRAM system is discussed along with a stacked FPGA and RRAM. Methods of system level design for 3D TSV stacked memory architectures are explored along with methods of designing a stacked heterogeneous TSV DRAM system. A cache architecture was used to configure stacked DRAM for specific applications. Methods of stacked 3D DRAM with embedded multicore DSPs are explored along with a network platform for stacked memory-processor architectures..

Section 11: Companies developing or producing 3D memories are discussed.

Section 12: Research Labs, Consortium and alliances for development and production of 3D memories are noted.

150+ pages.



Vertical (3D) Memories, April 2012

Table of Contents

Executive Summary

0.0 Overview of Vertical Memories

1.0 Vertical Pillar Gates and Vertical Access Transistors

2.0 FinFET and Trigate Nanowire Memories

3.0 Double Gate and Hybrid NV Memories and Vertical Channel

4.0 Nanowire High Density Memories

5.0 Integrated Process Stacking of NAND Chains

6.0 Stacked and Cross-Bar Array Memory Cells

7.0 Integration of Memory in the Interconnect Structure

8.0 3-D Stacking of Memory Using Through Silicon Vias (TSV)

9.0 Memory Stacking Using AC Inductive Coupling

10.0 Configuring Stacked TSV Memory Systems

11.0 Companies Developing and Supplying Vertical Memories

12.0 Research Cooperatives, Consortiums and Labs Working with 3D Technology



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