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Vertical (3D) Memories, April 2011
(Vertical Channels and Pillars, Double Gates, Cross-Point Arrays, 3D Stacking with TSV, Single Crystal Stacking, Vertical NAND Strings, Inductive Coupling)

This report on vertical and 3-D memories traces the emerging trend of using the vertical dimension on the memory chip rather than doing increasingly difficult scaling in the planar dimension. Vertical pillar memories (GAA) are discussed followed by vertical channels and double and triple gates. Cross-point stacked memories permit multiple layers of stacking in the fabrication process as do vertical NAND strings which use pillars and vertical stacks in various combinations. Through Silicon Vias (TSV) permit stacking of varying types of substrates such as memory and processors. Inductive coupling between stacked layers of memory is followed by discussion of other multiple substrate integration. 90+ pages.

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Table of Contents

Executive Summary

1.0 Vertical Pillar Gates

• 1.1 Multibit ProgramVertical Channel Si NW Flash Memory(Nanyang Tech U, A*STAR)
• 1.2 Vth Shift Characteristics of Gate-All-Around SONOS/TANOS NV(Seoul Nat. Univ.)
• 1.3 Cone-Type SONOS Cell for Improved Performance Characteristics (Seoul Nat. Univ.)
• 1.4 3D NVM in a Twin- Bit Pillar Structure with Common Control Gate (Seoul Nat. Univ.)
• 1.5 3D Flash Using Gate-All-Around SONOS memory with Vertical Si Nanowire (A-Star)
• 1.6 Bit-Cost Scalable Floating Pillar ONON Flash Memory (Toshiba)
• 1.7 High-k Al2O3 as Blocking Oxide for 3-D Self-Assembled NC Memory (U. of Texas)
• 1.8 50 nm Node Surrounding Gate Transistor NOR Flash (Tohoku U.)
  

2.0 Vertical Channel, Double Gate and FinFET Memories

• 2.1 Bandgap Engineered (BE) Folded Vertical Channel NAND (Seoul Nat. U., Stanford U.)
• 2.2 Vertical Channel BE-SONOS NAND Flash (Seoul National Univ.)
• 2.3 Retention times of 10s for bulk FinFET 1T-DRAM Devices (IMEC)
• 2.4 Vertical Double Gate "Z-RAM" Technology with Low Voltage Operation(Hynix, ISI)
• 2.5 Multi-Level Cell STT-MRAM with Series Connected MTJs (Hitachi, Tohoku U.)
• 2.6 A Silicon on Replacement Insulator FB-Cell Memory on Bulk Substrate (Intel)
• 2.7 Capacitorless Double Gate Quantum Well 1T eDRAM
• 2.8 Unified RAM with Poly-Channel TFT with Separated Double Gate (KAIST and Hynix)
• 2.9 Double Gate 1T DRAM with NV Function (Kyungpook Nat.U., Keoul Nat. U)
• 2.10 Floating Body Cell on Bulk Silicon Using 3D Structures (Innovative Silicon, Hynix)
• 2.11 Effect of FinFET Transistors Used for FB-RAM Operation on SOI (Vanderbilt U.)
• 2.12 Isolation Dielectric Effects of PDSOI FinFET on Capacitorless 1T-DRAM (KAIST)
• 2.13 Dopant Segregated Schottky Barrier FinFET Flash
  • 2.13.1 DSSB SONOS FinFET Flash for MLC Operation (KAIST, ETRI)
  • 2.13.2 Narrower Fin Width Using DSSB Technology for NOR Flash (KAIST)
  • 2.13.3 DSSB FinFET SONOS NOR Flash (KAIST, EECS, ETRI)
• 2.14 Vertical Double Gate Floating Body Device (Intel)
• 2.15 50 nm Double Gate 64 Cell 3D TFT SONOS (Schiltron)

3.0 3-D Stacking of Memory using Through Silicon Vias (TSV)

• 3.1 3D Stacking Integration for 28 nm CMOS Foundry Technology (TSMC)
• 3.2 Through Silicon Via Interconnects Under the Bond Pads on NAND Flash (ASTRI)
• 3.3 8-Gb DDR3 SDRAM Using TSV (Samsung)
• 3.4 Multistrata DRAM Stacked Fast CMOS Logic Using TSV and Organic Interposer (NEC)
• 3.5 Overview of 3D Wafer Bonding Technologies for Advanced Stacking Systems (ITRI)
• 3.6 Wafer Level 3D Integration using Adhesive Injection (Tohoku University)
• 3.7 3D Stacking of eDRAM L3 Cache over Processor with TSV (IBM)
• 3.8 3D Stacking of MRAMs on Chip Multiprocessors (Penn State Univ.)
• 3.9 Fabrication of TSV for Stacked Memory Chips(Tohoku University)
• 3.10 3D Reconfigurable Logic Block with SPRAM with TSV (Hitachi and Tohoku Univ.)

4.0 Integrated Process Stacking of NAND Chains

• 4.1 Vertical Gate TFT NAND Flash Buried Channel BE-SONOS Array (Macronix)
• 4.2 3-D Vertical Cylindrical Floating Gate NAND Cell Structure (Tohoku University)
• 4.3 3D TCAD Simulations of Vertical NAND Flash Architectures (Macronix)
• 4.4 3-D Stacked NAND Flash String Using Common Gate and Shield(Seoul Nat. U.)
• 4.5 Bit Cost Scalable (BiCS) Charge Trapping Pipe NAND Flash Technology (Toshiba)
  • 4.5.1 Improved Piped BiCS NAND Flash Technology (Toshiba)
  • 4.5.2 Bit-Cost Scalable Floating Pillar Vertical SONOS NAND Flash Memory (Toshiba)
  • 4.5.3 Bit-Cost Scalable Vertical SONOS NAND Flash Memory (Toshiba)
  • 4.5.4 Multi-level 32-Gb Pipe-Shaped BiCS NAND Flash Memory (Toshiba)
• 4.6 Vertical NAND TCAT (Samsung)
  • 4.6.1 Damascene W Metal Gate SONOS Vertical NAND Flash String"TCAT"(Samsung)
  • 4.6.2 Damascened Metal Gate SONOS Vertical NAND Flash String "TCAT" (Samsung)
  • 4.6.3 Vertical NAND Chains "VSAT" with "PIPE" Process (Samsung)
  • 4.6.4 3-D NAND Flash SONOS "VRAT" Using Planarized Integration (Samsung, UCLA)
• 4.7 Pipe Stacked NAND Flash (Hynix)
  • 4.7.1 3-D PipeFloating Gate NAND Flash Cell (Hynix)
• 4.8 Single Crystal Silicon Stacking
  • 4.8.1 3-D Stacked NAND Flash with Single Crystal Si Channel Body Stacks (Seoul Nat. U.)
  • 4.8.2 3-D DDR SRAM Using Laser Epi Crystalline Silicon Growth Technology (Samsung)
  • 4.8.3 3-D Stacked 45 nm NAND Flash using Single Crystal Silicon Stacking (Samsung)

5.0 Stacked and Cross-Point Memory Cells

• 5.1 Cross-Point CNT ReRAM(Stanford, H.K.U. of Sci&Tech., U.of C.,Berkeley, H.K. Polytech)
• 5.2 Characteristics of Cross-Point Memory Arrays without Cell Selectors (Stanford)
• 5.3 Operation of an RRAM Array Built in CMOS Metallization (Unity Semiconductor)
• 5.4 Stacking PCM in Cross-Point Array with Ovonic Threshold Switch (Intel, Numonyx)
• 5.5 3-D Cross-Point Memristor Technology (Hewlett-Packard Labs)
• 5.6 Eight Layer Stack of Cross-Point ReRAM Cells (Fudan Univ.)
• 5.7 Cross-Point PCM Using Polysilicon Selection Diode (Hitachi)
• 5.8 Vertical Cross-Point NiO Transition Metal Oxide RRAM (Samsung)
• 5.9 Improved Conduction Path Confinement for 3D NiO ReRAM Cell (Stanford U.)
• 5.10 Characterization of NiO RRAM in Low Resistance State (Politechnico di Milano)
• 5.11 Model for Physical Switching Mechanism in NiO Memory (Politechnico di Milano)
• 5.12 Stacked 3-D NiO RRAM with CuO diode and GIZO peripheral TFT (Samsung)
• 5.13 Phase Change Memory Cross-Point Cell with Doped Ge Nanowire Diodes (Stanford)
• 5.14 Physical model for PCM with Diode Access Device (HKUST)

6.0 Integration of Memory in the Interconnect Structure

• 6.1 SiO ReRAM in SiO with Cu and W Electrodes (Peking U. & U.of Calif, Riverside)
• 6.2 Solid Electrolyte Switch Embedded in Copper Interconnect (NEC)
• 6.3 Integration of NiO Memory Structures in Interconnect Structures (U. of Sud Toulon)
• 6.4 ReRAM Made with NiO Doped with Ti:NiO (Fujitsu)

7.0 Memory Stacking Using AC Inductive Coupling

• 7.1 Inductive Coupling to Replace TSV in Low Power CMOS Integration (Keio Univ.)
• 7.2 New Channel Coil Method for Inductive-Coupling of NAND Flash Stacks (Keio U.)
• 7.3 Processor/SRAM 3-D Integration Using Inductive-Coupling (Hitachi, Renesas, KeioU)
• 7.4 2Gb Inductive Coupling for 128 Die NAND Flash Stacking (Keio University)
• 7.5 Inductive Coupling Programmable Bus for NAND Flash in SSD(Keio U.,U.of Tokyo)
• 7.6 SRAM & Processor Integration Using Inductive Coupling (Renesas, Hitachi, Keio U.)
• 7.7 Stacked MPU/SRAM Inductive Coupled by Through Wire (Hitachi, Renesas, Keio U)

8.0 Chip Stacking using Configurable Memory

• 8.1 Dynamic Configurable SRAM Stacked with Various Logic Chips (NEC)
• 8.2 Stacked Flexible Configuration Memory (NEC)

9.0 Companies Developing and Supplying Vertical Memories

• 9.1 Fujitsu
• 9.2 Hitachi
• 9.3 IBM
• 9.4 Intel
• 9.5 Macronix
• 9.6 NEC
• 9.7 Renesas/Hitachi
• 9.8 Samsung
• 9.9 Toshiba
• 9.10 TSMC

10.0 Research Cooperatives and Labs Working with 3D Memory Technology

• 10.1 IMEC
• 10.2 A-Star
• 10.3 KAIST, EECS, ETRI
• 10.4 Hewlett-Packard Labs
• 10.5 Schiltron
• 10.6 Rensselaer Poly
• 10.7 ITRI

Bibliography

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