MEMORY STRATEGIES INTERNATIONAL Semiconductor Memory Services
| Home | Reports | Seminars | Consulting | Contact Us | About Us | See Our Memory Technology Reports on: 3D TSV DRAM | 3D NAND Flash | 3D ReRAM/Cross Point Array | Gate All Around | Embedded Flash | Resistance RAM | Embedded DRAM | MRAM | Ferroelectric | Nanocrystal Flash |

CONTENTS | TO ORDER

Vertical (3D) Memories, April 2012
(Vertical Channels & Pillars, FinFet, Tri-Gate, Double Gate, Cross-Bar Arrays, 3D Stacking with TSV, 3D TSV Configuration, Single Crystal Stacking, Vertical NAND Strings, Inductive Coupling )

This report on vertical and 3-D memories traces the emerging trend of using the vertical dimension on the memory chip rather than doing increasingly difficult scaling in the planar dimension.

Section 1:Three dimensional memories have been made for some time using vertical pillar gates. These include the surrounding gate, or gate-all-around flash memories. Vertical pillar flash memories are made using a SONOS deposition process and also using a nanocrystal self assembly process. Phase change memories are made with vertical acess device. 4F2 DRAMs are made with vertical pillar transistors. Dual pillar vertical STT-MRAMs are also being developed.

Section 2: FinFETs with thin vertical channels provide density and multiple bits in a small area. They are in advanced development for use in SRAMs. They have been used in floating body 1T-DRAM development and in floating gate and SONOS flash development. They improve short channel effects and increase the density of both non-volatile memories and SRAMs. Multigate nanowire memories are also in development as charge trapping flash memories of both the SONOS and nanocrystal types. There is indication FinFETs will enter production between 22nm and 14 nm.

Section 3: Double gate devices have improved gate control in scaled devices. Several vertical double gate SONOS devices have been discussed along with a double gate SONOS device in which the second gate was common to several devices. A vertical bridge NV cell used electrical isolation by a vertical pn junction. A hybrid dual gate TFT memory was suggested for large area electronics on flexible substrates. A double heterojunction bipolar transistor capacitorless 1T DRAM with a narrow bandgap SiGe body was also discussed along with a hybrid ferroelectric and Charge based NV memory.

Section 4: Nanowire high density memories can be stacked as 3-D NAND Flash. Junctionless GAA SONOS silicon horizontal nanowire was stacked as well as with vertical silicon nanowire.

Section 5: NAND chains have been stacked as pipes, as vertical trenches and through hole structures, with shield layers. Extended sidewall control gates have been added on vertical stacked NAND structures with separated sidewall control gates. Thin body charge trapping vertical gate NAND flash devices have been shown with improved sensing. Horizontal channel with vertical gate BE-SONOS NAND flash devices have been stacked with self-aligned PN diodes on the source side and also without the PN diodes. A hybrid 3D NAND flash cell with low address selection for stacked channels were shown which were suitable for NAND page operation.

Section 6: Several types of cross-bar array memories have been discussed. An electromechanical diode cell was shown, as was a CMOS memristor cross-bar array for neuromorphic architectures An organic memory cross bar array had graphene electrodes. A ZnO RRAM crossbar array was studied for sneak current.

Section 7: This section discussed memories which can be embedded in the interconnect structure normally in the back end of the line.

Section 8: Through-Silicon-Via (TSV) technology is proving it can provide high density memory arrays without the need for scaling the technology. These TSV connections appear key to future 3-D integration of substrates. Two approaches are currently being explored. One is "via-middle" schemes in which TSV are formed after the transistors are made but before BEOL processing. These vias have diameters from 5 um to 10 um with aspect ratios > 10:1. The other approach is the "via-last scheme" where TSVs are etched from the back side of a thinned wafer after BEOL completion. These vias are > 40 um with aspect ratios < 10:1. Chips connected with TSV can bring significant memory bandwidth in a small footprint for handheld tablets and smart phones. This can implement software applications such as HD Video, 3D Gaming, computing and image processing. This bandwidth can be provided by Through-Silicon Via (TSV) technology which connects the DRAM I/O vertically through the silicon with the processor bus in a processor-DRAM chip stack. TSV technology reduces connection capacitance and connection length. 124]

Section 9: Memory and processor stacking using inductive coupling connects is discussed.

Section 10: TSV stacked memory system require a different architecture configuration from standalone memory and processor chips in order to make the best use of the many high bandwidth connections. A 3.9 DGIP/W TSV stacked SRAM system is discussed along with a stacked FPGA and RRAM. Methods of system level design for 3D TSV stacked memory architectures are explored along with methods of designing a stacked heterogeneous TSV DRAM system. A cache architecture was used to configure stacked DRAM for specific applications. Methods of stacked 3D DRAM with embedded multicore DSPs are explored along with a network platform for stacked memory-processor architectures..

Section 11: Companies developing or producing 3D memories are discussed.

Section 12: Research Labs, Consortium and alliances for development and production of 3D memories are noted.

150+ pages.

DESCRIPTION | TO ORDER

Table of Contents

Executive Summary

0.0 Overview of Vertical Memories

1.0 Vertical Pillar Gates and Vertical Access Transistors

• 1.1 Vertical Diode for Using with Phase Change Memory (Samsung, Sungkyunkwan U.)
• 1.2 GAA SNW Junction-Less SONOS NAND(A*STAR,Nanyang,PekingU,GlobalFound.)
• 1.3 Vertical Cylindrical SONOS NAND with Bilayer Poly-si Channel (IMEC,ASM)
• 1.4 4F2 DRAM Cell with Vertical Pillar Transistor (Samsung)
• 1.5 4F2 40 nm 10fF Stacked DRAM with Vertical Access Transistor (Hitachi)
• 1.6 Dual Pillar STT-MRAM with Tilted Magnetic Anisotropy (Purdue University)
• 1.7 Poly Channel Vertical Flash for 3D SONOS NAND (IMEC, ASM, John Moores U.)
• 1.8 Vertical Si Nanowire GAA Memory Using Si NC (A*STAR, Nanyang U, U of Bologna)
• 1.9 Junction-Less 3D Stacked SiNW SONOS(A*STAR, Nanyang U, Global Foundries)
• 1.10 Vth Shift Characteristics of Gate-All-Around SONOS/TANOS NV(Seoul Nat. Univ.)
• 1.11 3D NVM in a Twin- Bit Pillar Structure with Common Control Gate (Seoul Nat. Univ.)
• 1.12 Cone-Type SONOS Cell for Improved Performance Characteristics (Seoul Nat. Univ.)

2.0 FinFET and Trigate Nanowire Memories

• 2.1 Overview of FinFET/Trigate
• 2.2 Trigate Nanowire Flash Memory with Si-NC CT Layer (NCTU, NTHU)
• 2.3 Trigate HfO2 Nanocrystal Memory on SOI (NUUM)
• 2.4 Trigate/FinFET Split-Gate Flash memory with Suppressed Over-Erase(Meiji U., AIST)
• 2.5 GHz 162 Mb 22 nm Tri-Gate High-K Metal Gate CMOS SRAM(Intel)
• 2.6 Noise in TFT SONOS Trigate Nanowires (NTUT, NTHU, and NNDL)
• 2.7 Vt of Poly-si Channel FinFET, Tri-Gate Flash and Crystal Channel Flash (AIST)
• 2.8 Grain Orientation Induced Variation in FinFETs (U. of Calif., N.C.K.U., A*STAR)
• 2.9 0.021 um2 10 nm Trigate SRAM Cell [IBM]
• 2.10 Effect of Substrate Bias on Characteristics of Bulk FinFET 1T-DRAM Cell (IMEC)
• 2.11 DSSB SONOS FinFET Flash for MLC Operation (KAIST, ETRI)
• 2.12 Retention times of 10s for bulk FinFET 1T-DRAM Devices (IMEC)
• 2.13 Narrower Fin Width Using DSSB Technology for NOR Flash (KAIST)
• 2.14 Effect of FinFET Transistors Used for FB-RAM Operation on SOI (Vanderbilt U.)
• 2.15 Isolation Dielectric Effects of PDSOI FinFET on Capacitorless 1T-DRAM (KAIST)
• 2.16 DSSB FinFET SONOS NOR Flash (KAIST, EECS, ETRI)

3.0 Double Gate and Hybrid NV Memories and Vertical Channel

• 3.1 Read Characteristics of Polysilicon NW Double Gate SONOS Devices (NCTU)
• 3.2 22 nm 1T eDRAM Cell With Body Partitioning Vertical PN Junction(U. of Granada)
• 3.3 Hybrid Dual-Gate Org/Inorg NV Memory TFT(Kyung Hee U, Elec.& Telecom Res.Inst.)
• 3.4 Double Heterojunction Vertical 1T DRAM with Si/SiGe Heterojunctions (Kookmin U.)
• 3.5 Hybrid Ferroelectric and Charge NV Memory (Cornell University)
• 3.6 Offset Buried MG Vertical FB Cell on Recess Gate DRAM Technology (Hynix)
• 3.7 A Dual Channel TFT - FeFET Used in NAND Type Memory (Panasonic)
• 3.8 Bandgap Engineered (BE) Folded Vertical Channel NAND (Seoul Nat. U., Stanford U.)
• 3.9 Ferroelectric Gate Thin Film Transistor (JAIST, ERATO)
• 3.10 Vertical Channel 1T-DRAM with Middle Partial Insulation (Nat. Sun Yat-Sen Univ.)
• 3.11 1T-DRAM Cell with Partitioned Body (Univ. de Granada)
• 3.12 Operation of Double Gate Bipolar Operation 1T DRAM cells (U. of Calabria)
• 3.13 Vertical Channel BE-SONOS NAND Flash (Seoul National Univ.)
• 3.14 Vertical Double Gate "Z-RAM" Technology with Low Voltage Operation(Hynix, ISI)
• 3.15 Multi-Level Cell STT-MRAM with Series Connected MTJs (Hitachi, Tohoku U.)
• 3.16 A Silicon on Replacement Insulator FB-Cell Memory on Bulk Substrate (Intel)
• 3.17 Capacitorless Double Gate Quantum Well 1T eDRAM
• 3.18 Unified RAM with Poly-Channel TFT with Separated Double Gate (KAIST and Hynix)
• 3.19 Double Gate 1T DRAM with NV Function (Kyungpook Nat.U., Keoul Nat. U)
• 3.20 Floating Body Cell on Bulk Silicon Using 3D Structures (Innovative Silicon, Hynix)

4.0 Nanowire High Density Memories

• 4.1 3-D Single Crystalline Stacked NAND Flash (STAR) (Seoul Nat. U., Samsung)
  • 4.1.1 3-D Stacked NAND Flash (STAR) 3-D TCAD Simulation (Seoul Nat. U., Samsung)
  • 4.1.2 Silicon Nanowire Stacked 3-D NAND Flash Process (Samsung, Seoul Nat. U.)
  • 4.1.3 Stacked Single Crystal Silicon NW NAND Flash Array (Samsung, Seoul Nat.U.)
• 4.2 Junctionless GAA SONOS Si NanoWire on Bulk for 3D Stacked NAND (KAIST)
• 4.3 Multibit ProgramVertical Channel Si NW Flash Memory(Nanyang Tech U, A*STAR)
• 4.4 3D Flash Using Gate-All-Around SONOS memory with Vertical Si Nanowire (A-Star)

5.0 Integrated Process Stacking of NAND Chains

• 5.1 3-D NAND Flash SB-CAT Stack (Seoul National University)
• 5.2 3-D Vertical FG NAND with Extended Sidewall Control Gate(Tohoku U., Hynix)
  • 5.2.1 3-D Vertical NAND with Extended Sidewall Control Gates (Tohoku U., Hynix)
  • 5.2.2 3-D Vertical Stacked FG NAND Array with No Interference(Tohoku U.,JST-CREST)
  • 5.2.3 3-D Vertical FG NAND with Separated-Sidewall Control Gate (Tohoku U., Hynix)
• 5.4 Read Sensing for Thin Body Vertical Gate NAND (Stanford U., Seoul Nat. Univ.)
• 5.5 Electrical Layer Selection in BL Stacked 3-D NAND Array (Samsung, Seoul Nat. U.)
• 5.6 Horizontal Channel VG 3D NAND Flash (Macronix)
  • 5.6.1 Horizontal Channel VG 3D NAND Flash with PN Diode Decoding (Macronix)
  • 5.6.2 Vertical Gate TFT NAND Flash Buried Channel BE-SONOS Array (Macronix)
• 5.7 3D NAND Flash with Horizontal Channel Vertical Gate Hybrid Structure (Hynix)
• 5.8 3D Vertical Pipe Low Resistance (CoSi) WL NAND Flash (Hynix)
• 5.9 Read for 3D Dual CG with Surround FG NAND (Hynix)
• 5.10 Advanced Process Technologies for Scaled NAND Flash < 20 nm (Applied Materials)
• 5.11 3-D Vertical Cylindrical Floating Gate NAND Cell Structure (Tohoku University)
• 5.12 3D TCAD Simulations of Vertical NAND Flash Architectures (Macronix)
• 5.13 3-D Stacked NAND Flash String Using Common Gate and Shield(Seoul Nat. U.)
• 5.14 Bit Cost Scalable (BiCS) Charge Trapping Pipe NAND Flash Technology (Toshiba)
  • 5.14.1 Improved Piped BiCS NAND Flash Technology (Toshiba)
  • 5.14.2 Bit-Cost Scalable Floating Pillar Vertical SONOS NAND Flash Memory (Toshiba)
  • 5.14.3 Bit-Cost Scalable Floating Pillar Vertical SONOS NAND Flash Memory (Toshiba)
  • 5.14.4 Multi-level 32-Gb Pipe-Shaped BiCS NAND Flash Memory (Toshiba)
• 5.15 Vertical NAND TCAT (Samsung)
  • 5.15.1 Damascene W Metal Gate SONOS Vertical NAND Flash String"TCAT"(Samsung)
  • 5.15.2 Damascened Metal Gate SONOS Vertical NAND Flash String "TCAT" (Samsung)
• 5.16 Pipe Stacked NAND Flash (Hynix)
  • 5.16.1 3-D Pipe Floating Gate NAND Flash Cell (Hynix)
• 5.17 Single Crystal Silicon Stacking
  • 5.17.1 3-D Stacked NAND Flash with Single Crystal Si Channel Body Stacks (Seoul Nat. U.)
  • 5.17.2 3-D Double Stacked DDR SRAM Using Laser Epi Crystal Silicon Growth (Samsung)

6.0 Stacked and Cross-Bar Array Memory Cells

• 6.1 Electromechanical Diode Cell for a Cross-Point NV Memory Array
• 6.2 CMOS Memristors for Neuromonphic Architectures (HRL Labs, U. of Michigan)
• 6.3 Organic Memory Cross-Bar Array with Graphene Electrode(Gwangju Inst.of S&T)
• 6.4 Heterostructure Diodes for Sneak Current in ZnO RRAM Crossbar Array(KAIST)
• 6.5 Unipolar NiO RRAM Ireset & SET-RESET Instability (Polit.diMilano, IMM-CNR)
• 6.6 Ni/Ox Anode for Unipolar HfOx RRAM For 3D Stacking (ITRI,NTHU,MingShinU)
• 6.7 High Yield Ni/HfOx/n+ Si RRAM Cross-Bar+ Si Diode (Nanyang,NUS Soitec,Fudan)
• 6.8 Ni/HfOx/n+ Si Unipolar RRAM Cross-Bar+ Si Diode (Nanyang,NUS Soitec,Fudan)
• 6.9 Peripheral Design for Cross Point Memristor-based RRAM (Penn. State Univ.)
• 6.10 TiO2 MIM Selection Device for TiO2 RRAM Cross-Point Array (Gwangju IST)
• 6.11 3D Bipolar ReRAM Forming Memory Islands (NYU)
• 6.12 BiLayer RRAM Devices in A Diode-Free Cross-Point Array (Gwangju Inst.of S&T)
• 6.13 4F2 CMOS Cross-Bar HfO2 ReRAM with Vertical BJT Access(NTHU, ITRI)
• 6.14 4F2 CMOS Cross-Bar HfO2 ReRAM with Vertical BJT Access(NTHU, ITRI)
• 6.15Cross-Point CNT ReRAM(Stanford,H.K.U. of Sci&Tech., U.of C.,Berkeley, H.K. Polytech)
• 6.16 ZrO2 Crossbar RRAM built on a foundry platform substrate (Chin. Acad. Of Sci)
• 6.17 Crossbar ZrO2 RRAM built on a foundry platform substrate (Chin. Acad. Of Sci)
• 6.18 Characteristics of Cross-Point Memory Arrays without Cell Selectors (Stanford)
• 6.19 Complementary ReRAM for Dense Crossbar Arrays(Inst. of SS,Julich,AachenU)
• 6.20 Operation of an RRAM Array Built in CMOS Metallization (Unity Semiconductor)
• 6.21 Stacking PCM in Cross-Point Array with Ovonic Threshold Switch (Intel, Numonyx)
• 6.22 3-D Cross-Point Memristor Technology (Hewlett-Packard Labs)
• 6.23 Eight Layer Stack of Cross-Point ReRAM Cells (Fudan Univ.)
• 6.24 Cross-Point PCM Using Polysilicon Selection Diode (Hitachi)
• 6.25 Vertical Cross-Point NiO Transition Metal Oxide RRAM (Samsung)
• 6.26 Improved Conduction Path Confinement for 3D NiO ReRAM Cell (Stanford U.)

7.0 Integration of Memory in the Interconnect Structure

• 7.1 HfO2-based Bipolar RRAM Integrated in BEOL (NTU, ITRI)
• 7.2 MIM eDRAM Capacitor in Low-K Film for 28 nm Logic Node (Renesas)
• 7.3 eDRAM Cell Architecture in 45 nm Technology Node (STMicroelectronics)
• 7.4 Improving Operating Margin for Ta2O5/Plasma oxidized TiO2 1T1R Cell (NEC)
• 7.5 SiO ReRAM in SiO with Cu and W Electrodes (Peking U. & U.of Calif, Riverside)
• 7.6 Solid Electrolyte Switch Embedded in Copper Interconnect (NEC)

8.0 3-D Stacking of Memory Using Through Silicon Vias (TSV)

• 8.1 Co-Optimized Model of 3D Controller and DRAM System (T.U. Kaiserslautern)
• 8.2 3D Chip Singapore TSV Packaging Lab (Applied Materials and A*STAR)
• 8.3 Stacked 130nm 64 Cores & 256 KB SRAM(Georgia IT, KAIST, Amkor,Tezzaron)
• 8.4 Prototyping Fab for TSV 3D Solutions (CEA-Leti)
• 8.5 DLL-Based Data Self-Aligner for TSV Interface for Stacked DRAM(Hynix, Korea U)
• 8.6 3D 45 nm Stacked eDRAM and Processor using uC4 and 20 um TSV(IBM)
• 8.7 Stacking 12.8 GB/s 1Gb Mobile x128 I/O SDRAM Using TSV (Samsung)
• 8.8 HMC DRAM Memory Cube with Middle VIA TSV (IBM, Micron)
• 8.9 Testing and Reliability of 3D Copper TSV DRAM integration (IBM)
• 8.10 4 TSV Via-Middle Process (IBM)
• 8.11 TSV Stacked Hybrid Memory Cube Colloboration (Samsung, Micron)
• 8.12 3D Stacked STT-MRAM in Multi-Core Processor Systems(IBM, PekingU, PennStateU)
• 8.13 Thermal and Mechanical Models for Optimizing 3D DRAM on Logic Stacks (IMEC)
• 8.14 3-D DRAM TSV Allocation and Decoupling Capacitor Strategy (Rensselaer Poly)
• 8.15 32 GB DDR3 RDIMM Using 3D TSV Stacking Technology (Samsung)
• 8.16 Characteristics of 3D Systems with Stacked DRAM (Boston U.)
• 8.17 Benefits of 3D TSV Processor and Memory Integration (IBM)
• 8.18 3D Stackable 32 nm Embedded DRAM with Copper TSV (IBM)
• 8.19 Thermal Energy Reduction for 3D Stacked L3 DRAM Cache Using ECC (KAIST)
• 8.20 Through Silicon Interposer Multi-Dies Stacking (UTAC, Singapore)
• 8.21 1-Gbit Terabyte/s DRAM Architecture Using TSV for 3-D Connects (Hitachi)
• 8.22 3-D Integration of Stacked DRAM with TSV for Mobile Aps (U. of Kaiserslautern)
• 8.23 Mobile DRAM with WideIO Interface Using TSV Stacking (Samsung)
• 8.24 Standard for WideIO Memory-Logic Stacked Cube (JEDEC JC42.6)
• 8.25 Modeling of Coupling Noise in 3-D ICs with TSV (Mentor Graphics,U.Calif.SB)
• 8.26 3D Stacking Integration for 28 nm CMOS Foundry Technology (TSMC)
• 8.27 8-GB RDIMM with TSV Die Stacking (Samsung)
• 8.28 Through Silicon Via Interconnects Under the Bond Pads on NAND Flash (ASTRI)
• 8.29 8-Gb DDR3 SDRAM Using TSV (Samsung)
• 8.30 Multistrata DRAM Stacked Fast CMOS Logic Using TSV and Organic Interposer (NEC)
• 8.31 Overview of 3D Wafer Bonding Technologies for Advanced Stacking Systems (ITRI)
• 8.32 Wafer Level 3D Integration using Adhesive Injection (Tohoku University)
• 8.33 3D Stacking of eDRAM L3 Cache over Processor with TSV (IBM)
• 8.34 Some Companies Making Tools for 3D TSV stacks:
• 8.34.1 Applied Materials
• 8.34.2 Novellus
• 8.34.3 EV Group

9.0 Memory Stacking Using AC Inductive Coupling

• 9.1 1 Coil per Channel Thru-Chip Inductive Coupling for NAND Stack (KeioU)
• 9.2 Inductive Coupling to Replace TSV in Low Power CMOS Integration (Keio Univ.)
• 9.3 New Channel Coil Method for Inductive-Coupling of NAND Flash Stacks (Keio U.)
• 9.4 Processor/SRAM 3-D Integration Using Inductive-Coupling (Hitachi, Renesas, KeioU)
• 9.5 2Gb Inductive Coupling for 128 Die NAND Flash Stacking (Keio University)
• 9.6 Inductive Coupling Programmable Bus for NAND Flash in SSD(Keio U.,U.of Tokyo)

10.0 Configuring Stacked TSV Memory Systems

• 10.1 Configurable 3.9DGIPs/W TSV Stacked System with 64 Cores&SRAM(U.of Michigan)
• 10.2 3D Stacked FPGA and RRAM Configuration Memory (Stanford U.)
• 10.3 3D IP Blocks for Design Reuse of 2D Memory/Logic Stacks (Dresden U. of Tech)
• 10.4 System Level Design for 3D TSV Stacked Memory Architecture (ITRI)
• 10.5 Designing a stacked heterogeneous TSV DRAM System (Intel, Georgia Inst. of Tech)
• 10.6 Cache Architecture to Configure Stacked DRAM to Specific Applications (Kyushu U.)
• 10.7 3D DRAM Stacking in Embedded Multi-Core DSP Application (ITRI, NTHU)
• 10.8 Increasing 3D Inter-Chip TSV Connections Using Multiplexed Signals (U. of Mass)
• 10.9 Network Platform for Stacked Memory-Processor Architectures (U. of Turku)
• 10.10 Evaluation of Stacking an MRAM Chip on top of a CMOS MPU (Penn State U.)
• 10.11 3-D Hybrid Cache with MRAM and SRAM Stacked on Processor Cores(Penn. State U.)
• 10.12 Performance Improvements in 3-D Stacked DRAM Utilization (Postech)
• 10.13 CMOS FPGA and Routing Switches Made with RRAM Devices
• 10.14 Dynamic Configurable SRAM Stacked with Various Logic Chips (NEC)

11.0 Companies Developing and Supplying Vertical Memories

• 11.1 Hitachi
• 11.2 SK Hynix
• 11.3 IBM
• 11.4 Intel
• 11.5 Macronix
• 11.6 Micron
• 11.7 NEC
• 11.8 Qualcomm
• 11.9 Panasonic
• 11.10 Renesas
• 11.11 Samsung
• 11.12 Toshiba

12.0 Research Cooperatives, Consortiums and Labs Working with 3D Technology

• 12.1 CEA-LETI
• 12.2 Micron and Samsung TSV 3D DRAM Alliance
• 12.3 Elpida, Powertech, UMC TSV Alliance
• 12.4 IMEC TSV Stacking
• 12.5 A*STAR
• 12.6 KAIST (EECS, ETRI)
• 12.7 Hewlett-Packard Labs
• 12.8 HMC Industry Consortium
• 12.9 ITRI
• 12.10 SEMATECH 3D Interconnect Program at U. Albany
• 12.11 University of Albany Nanocollege

Bibliography

DESCRIPTION | CONTENTS

To order "Vertical (3D) Memories, April 2012":

Contact Memory Strategies or
Send us the information requested below by e-mail, fax, or post along with your check, bank transfer, or purchase order for $975. ($850 if a Memory Technology Report has been ordered from Memory Strategies in the past year.)

ORDER FORM: 
Please send ______ copies of  "Vertical (3D) Memories 2012" to:

Report Format

____ PDF. Will be sent by email. Please send your order by email, if possible. Printing hardcopy from PDF is permitted.

Submit Order and Payment Information via:
    Email: info@memorystrategies.com, or
    Fax:    +1 512 900 2846
    Post:
        Memory Strategies International,
        16900 Stockton Drive,
        Leander, Texas 78641, U.S.A.

To pay by:

• Credit Card: please fax credit card information to +1 512 900 2846
• Bank Transfer: please send in your order and request transfer details.
• Purchase Order: submit purchase order details with order.

For more information, please Contact Memory Strategies

| Home | Reports | Seminars | Consulting | Contact Us | About Us |

Memory Strategies International, 16900 Stockton Drive, Leander, TX, USA, 78641;   512.260.8226 (phone), 512.900.2846 (fax). Send questions or comments about this website to webmaster@memorystrategies.com. Copyright © 2015 Memory Strategies International. All rights reserved. Legal stuff. Last Modified: June, 2015.